Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git] / passes / memory / memory_collect.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-21 Clifford WolfMerge pull request #758 from whitequark/tcl_script_args
2018-12-21 Clifford WolfMerge pull request #759 from whitequark/memory_collect_...
2018-12-21 whitequarkmemory_collect: do not truncate 'x from \INIT.
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-08-19 Clifford WolfOptimize memory address port width in wreduce and memor...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-09 Clifford WolfUse MEMID as name for $mem cell
2015-07-06 Clifford WolfDo not collect disabled $memwr cells
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-05 Clifford WolfAvoid parameter values with size 0 ($mem cells)
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-14 Clifford WolfVarious fixes for memories with offsets
2015-02-14 Clifford WolfAdded $meminit support to "memory" command
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfChanges to "memory" pass for new $memwr/$mem WR_EN...
2014-02-08 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-08 Clifford WolfFixed bug in collecting of RD_TRANSPARENT parameter...
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfAdded correct handling of $memwr priority
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method
2013-03-01 Clifford WolfAdded help messages to memory_* passes
2013-01-05 Clifford Wolfinitial import