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Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git]
/
passes
/
memory
/
memory_dff.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2018-12-22
Clifford Wolf
Merge pull request #757 from whitequark/manual_mem
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2018-12-19
Clifford Wolf
Merge pull request #752 from Icenowy/anlogic-lut-cost
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2018-12-19
Clifford Wolf
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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2018-12-19
Clifford Wolf
Merge pull request #749 from Icenowy/anlogic-dram-fix
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-12-18
Clifford Wolf
Merge pull request #748 from makaimann/add-btor-ops
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2018-12-18
Clifford Wolf
Merge pull request #751 from daveshah1/fix_589
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2018-12-18
David Shah
memory_dff: Fix typo when checking init value
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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2018-07-04
Aman Goel
Merging with official repo
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2018-05-28
Clifford Wolf
Disable memory_dff for initialized FFs
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2016-02-13
Clifford Wolf
Fixed some visual studio warnings
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-31
Clifford Wolf
Bugfix in memory_dff
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-14
Clifford Wolf
Modernized memory_dff (and fixed a bug)
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2015-06-09
Clifford Wolf
Merge clock inverters in memory_dff
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-16
Clifford Wolf
Fixed $memwr/$memrd order in memory_dff
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2014-08-06
Clifford Wolf
Various improvements in memory_dff pass
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Using new obj iterator API in a few places
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-23
Clifford Wolf
Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-06-01
Clifford Wolf
Fixed log messages in memory_dff
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2013-12-01
Clifford Wolf
A fix in memory_dff for write ports with static addresses
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2013-03-01
Clifford Wolf
Added help messages to memory_* passes
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2013-01-05
Clifford Wolf
initial import
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