Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git] / passes / memory / memory_dff.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops
2018-12-18 Clifford WolfMerge pull request #751 from daveshah1/fix_589
2018-12-18 David Shahmemory_dff: Fix typo when checking init value
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-05-28 Clifford WolfDisable memory_dff for initialized FFs
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-02-13 Clifford WolfFixed some visual studio warnings
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-31 Clifford WolfBugfix in memory_dff
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-14 Clifford WolfModernized memory_dff (and fixed a bug)
2015-06-09 Clifford WolfMerge clock inverters in memory_dff
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-16 Clifford WolfFixed $memwr/$memrd order in memory_dff
2014-08-06 Clifford WolfVarious improvements in memory_dff pass
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-06-01 Clifford WolfFixed log messages in memory_dff
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2013-12-01 Clifford WolfA fix in memory_dff for write ports with static addresses
2013-03-01 Clifford WolfAdded help messages to memory_* passes
2013-01-05 Clifford Wolfinitial import