git.libre-soc.org Git - yosys.git/history - passes/memory/memory

[yosys.git] / passes / memory / memory_map.cc

2019-03-28	Benedikt Tutzer	Merge remote-tracking branch 'origin/master' into featu...	blob \| commitdiff \| raw
2018-09-17	Udi Finkelstein	Merge branch 'master' into pr_reg_wire_error	blob \| commitdiff \| raw
2018-08-22	Jim Lawson	Merge pull request #1 from YosysHQ/master	blob \| commitdiff \| raw
2018-08-18	Aman Goel	Merge pull request #3 from YosysHQ/master	blob \| commitdiff \| raw
2018-08-15	Clifford Wolf	Merge pull request #573 from cr1901/msys-64	blob \| commitdiff \| raw
2018-08-15	Clifford Wolf	Merge pull request #591 from hzeller/virtual-override	blob \| commitdiff \| raw
2018-07-21	Henner Zeller	Consistent use of 'override' for virtual methods in...	blob \| commitdiff \| raw
2016-07-08	Clifford Wolf	Merge branch 'yosys-0.5-vtr' of https://github.com...	blob \| commitdiff \| raw \| diff to current
2016-04-23	Andrew Zonenberg	Merge https://github.com/cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2016-04-21	Clifford Wolf	Added "yosys -D" feature	blob \| commitdiff \| raw \| diff to current
2015-12-07	Clifford Wolf	Merge pull request #108 from cseed/master	blob \| commitdiff \| raw \| diff to current
2015-09-25	Clifford Wolf	Added read-enable to memory model	blob \| commitdiff \| raw \| diff to current
2015-07-02	Clifford Wolf	Fixed trailing whitespaces	blob \| commitdiff \| raw \| diff to current
2015-04-05	Clifford Wolf	Avoid parameter values with size 0 ($mem cells)	blob \| commitdiff \| raw \| diff to current
2015-04-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2015-02-14	Clifford Wolf	Various fixes for memories with offsets	blob \| commitdiff \| raw \| diff to current
2015-02-14	Clifford Wolf	Added $meminit support to "memory" command	blob \| commitdiff \| raw \| diff to current
2014-10-10	Clifford Wolf	Renamed SIZE() to GetSize() because of name collision...	blob \| commitdiff \| raw \| diff to current
2014-09-27	Clifford Wolf	namespace Yosys	blob \| commitdiff \| raw \| diff to current
2014-09-22	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-08-30	Clifford Wolf	Improved write address decoder generation memory_map	blob \| commitdiff \| raw \| diff to current
2014-08-30	Clifford Wolf	Using worker class in memory_map	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	More cleanups related to RTLIL::IdString usage	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Renamed port access function on RTLIL::Cell, added...	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Moved some stuff to kernel/yosys.{h,cc}, using Yosys...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Using log_assert() instead of assert()	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Refactoring: Renamed RTLIL::Design::modules to modules_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::cells to cells_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::wires to wires_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed a lot of code to the new RTLIL::Wire constructors	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Merge automatic and manual code changes for new cell...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed users of cell->connections_ to the new API...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Renamed RTLIL::{Module,Cell}::connections to connections_	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Use only module->addCell() and module->remove() to...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: using the accessor functions every...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: renamed chunks and width to __chun...	blob \| commitdiff \| raw \| diff to current
2014-07-16	Clifford Wolf	Merged new $mem/$memwr WR_EN interface	blob \| commitdiff \| raw \| diff to current
2014-07-16	Clifford Wolf	Changes to "memory" pass for new $memwr/$mem WR_EN...	blob \| commitdiff \| raw \| diff to current
2014-02-03	Clifford Wolf	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...	blob \| commitdiff \| raw \| diff to current
2014-02-02	Clifford Wolf	Only generate write-enable $and if WE is not constant...	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced RTLIL::Const::str with generic decoder method	blob \| commitdiff \| raw \| diff to current
2013-10-17	Clifford Wolf	Fixed bug in synthesis of memories that are never written	blob \| commitdiff \| raw \| diff to current
2013-03-01	Clifford Wolf	Added help messages to memory_* passes	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current

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