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memory_share: Don't skip ports with EN wired to input for SAT sharing.
[yosys.git]
/
passes
/
memory
/
memory_share.cc
2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-23
Clifford Wolf
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-07-21
Clifford Wolf
Removed deprecated module->new_wire()
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2014-07-19
Clifford Wolf
Improved memory_share log messages
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2014-07-19
Clifford Wolf
More verbose memory_share help message
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2014-07-19
Clifford Wolf
Added SAT-based write-port sharing to memory_share
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2014-07-19
Clifford Wolf
Fixed bug in memory_share feedback-to-en code
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2014-07-18
Clifford Wolf
Added translation from read-feedback to en-signals...
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2014-07-18
Clifford Wolf
Only create collision detect logic in memory_share...
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2014-07-18
Clifford Wolf
Added memory_share
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projects / yosys.git / history