Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git] / passes / memory / memory_unpack.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-14 Larry DoolittleKeep gcc from complaining about uninitialized variables
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-29 Clifford WolfFixed memory_unpack for initialized memories
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfChanges to "memory" pass for new $memwr/$mem WR_EN...
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge pull request #3 from cliffordwolf/master
2014-01-16 Clifford WolfAdded automatic memid generation to memory_unpack command
2014-01-16 Clifford WolfAdded memory_unpack command