Improve opt_clean handling of unused wires
[yosys.git] / passes / opt / opt_clean.cc
2019-05-04 Clifford WolfImprove opt_clean handling of unused wires
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-03 Clifford WolfMerge pull request #985 from YosysHQ/clifford/fix981
2019-05-03 Clifford WolfImprove opt_expr and opt_clean handling of (partially...
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-29 Clifford WolfDrive dangling wires with init attr with their init...
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Clifford WolfAdd log_debug() framework
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-13 Clifford WolfMerge pull request #468 from grahamedgecombe/fix-sb...
2017-12-12 Clifford WolfAdd warnings for driver-driver conflicts between FFs...
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-10-26 Clifford WolfFix typo in opt_clean log message
2017-07-28 Clifford WolfAdd consolidation of init attributes to opt_clean,...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2016-08-28 Clifford WolfRemoved $predict again
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-26 Clifford WolfConnections between inputs and inouts are driven by...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-02-02 Clifford WolfUse alphanumerical order instead of idstring idx in...
2015-08-16 Clifford WolfFixed opt_clean handling of inout ports
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-12 Clifford WolfImproved handling of "keep" attributes in hierarchical...
2015-08-12 Clifford WolfMerge pull request #70 from gaomy3832/bugfix
2015-08-11 Mingyu GaoRemove unused blackbox modules in opt_clean.
2015-08-11 Clifford WolfAdded missing ct_all setup to opt_clean
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-05-22 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-05-22 Clifford Wolfpreserve used $-wires with init attribute in opt_clean
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-24 Clifford WolfSome cleanups in "clean"
2015-02-14 Clifford WolfAdded $meminit cell type
2015-02-04 Clifford WolfFixed opt_clean performance bug
2015-02-03 Clifford WolfUsing design->selected_modules() in opt_*
2015-01-23 Clifford WolfAdded dict/pool.sort()
2014-12-29 Clifford WolfCleanups in opt_clean
2014-12-29 Clifford Wolfdict/pool changes in opt_clean
2014-12-28 Clifford WolfRenamed hashmap.h to hashlib.h, some related improvements
2014-12-27 Clifford WolfMore hashtable finetuning
2014-12-26 Clifford WolfReplaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-10-18 Clifford WolfFixed various VS warnings
2014-10-16 Clifford WolfSome cleanups in opt_clean
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-10-03 Clifford WolfAdded $_BUF_ cell type
2014-10-03 Clifford Wolfremove buffers in opt_clean
2014-09-29 Clifford WolfAdded support for "keep" on modules
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-15 Clifford WolfMore idstring sort_by_* helpers and fixed tpl ordering...
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfAdded SigPool::check(bit)
2014-07-27 Clifford WolfFixed bug in opt_clean
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
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