More hashtable finetuning
[yosys.git] / passes / opt / opt_clean.cc
2014-12-27 Clifford WolfMore hashtable finetuning
2014-12-26 Clifford WolfReplaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-10-18 Clifford WolfFixed various VS warnings
2014-10-16 Clifford WolfSome cleanups in opt_clean
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-10-03 Clifford WolfAdded $_BUF_ cell type
2014-10-03 Clifford Wolfremove buffers in opt_clean
2014-09-29 Clifford WolfAdded support for "keep" on modules
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-15 Clifford WolfMore idstring sort_by_* helpers and fixed tpl ordering...
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfAdded SigPool::check(bit)
2014-07-27 Clifford WolfFixed bug in opt_clean
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-16 Clifford WolfFixed handling of "keep" attribute on wires in opt_clean
2014-02-08 Clifford WolfOnly count non-trivial attributes when findinf master...
2014-02-07 Clifford WolfImproved detection of primary wire for a signal in...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert cell
2013-11-08 Clifford WolfFixed keep attribute on wires in opt_clean
2013-11-05 Clifford WolfAdded support for "keep" attributes on wires
2013-10-24 Clifford WolfFixed handling of boolean attributes (passes)
2013-10-17 Clifford WolfOnly prefer connected signals iff they have public...
2013-10-17 Clifford WolfAvoid re-arranging signals on register outputs
2013-10-17 Clifford WolfFixed detection of major wires in opt_clean
2013-10-16 Clifford WolfAdded iopadmap pass
2013-08-11 Clifford WolfAdded "clean -purge" and ";;;" support
2013-08-11 Clifford WolfAdded ";;" as shortcut for "; clean;"
2013-08-09 Clifford WolfSome fixes to improve determinism
2013-08-08 Clifford WolfAdded "clean" command (less verbose opt_clean)
2013-08-07 Clifford WolfImproved handling of private names in opt_clean and...
2013-07-07 Clifford WolfAdded opt_clean -purge option
2013-06-05 Clifford WolfRenamed opt_rmunused to opt_clean