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More hashtable finetuning
[yosys.git]
/
passes
/
opt
/
opt_clean.cc
2014-12-27
Clifford Wolf
More hashtable finetuning
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2014-12-26
Clifford Wolf
Replaced std::unordered_set (nodict) with Yosys::pool
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2014-12-26
Clifford Wolf
Added Yosys::{dict,nodict,vector} container types
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2014-10-18
Clifford Wolf
Fixed various VS warnings
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2014-10-16
Clifford Wolf
Some cleanups in opt_clean
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-10-03
Clifford Wolf
Added $_BUF_ cell type
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2014-10-03
Clifford Wolf
remove buffers in opt_clean
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2014-09-29
Clifford Wolf
Added support for "keep" on modules
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-09-06
Clifford Wolf
Merge pull request #38 from rubund/master
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2014-09-06
Ruben Undheim
Corrected spelling mistakes found by lintian
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2014-08-30
Clifford Wolf
Added design->scratchpad
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2014-08-15
Clifford Wolf
More idstring sort_by_* helpers and fixed tpl ordering...
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2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Added SigPool::check(bit)
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2014-07-27
Clifford Wolf
Fixed bug in opt_clean
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2014-07-27
Clifford Wolf
Fixed a bug in opt_clean and some RTLIL API usage cleanups
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::expand() method
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2014-07-23
Clifford Wolf
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-02-16
Clifford Wolf
Fixed handling of "keep" attribute on wires in opt_clean
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2014-02-08
Clifford Wolf
Only count non-trivial attributes when findinf master...
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2014-02-07
Clifford Wolf
Improved detection of primary wire for a signal in...
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-19
Clifford Wolf
Added $assert cell
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2013-11-08
Clifford Wolf
Fixed keep attribute on wires in opt_clean
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2013-11-05
Clifford Wolf
Added support for "keep" attributes on wires
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (passes)
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2013-10-17
Clifford Wolf
Only prefer connected signals iff they have public...
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2013-10-17
Clifford Wolf
Avoid re-arranging signals on register outputs
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2013-10-17
Clifford Wolf
Fixed detection of major wires in opt_clean
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2013-10-16
Clifford Wolf
Added iopadmap pass
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2013-08-11
Clifford Wolf
Added "clean -purge" and ";;;" support
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2013-08-11
Clifford Wolf
Added ";;" as shortcut for "; clean;"
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2013-08-09
Clifford Wolf
Some fixes to improve determinism
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2013-08-08
Clifford Wolf
Added "clean" command (less verbose opt_clean)
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2013-08-07
Clifford Wolf
Improved handling of private names in opt_clean and...
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2013-07-07
Clifford Wolf
Added opt_clean -purge option
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2013-06-05
Clifford Wolf
Renamed opt_rmunused to opt_clean
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