Merge branch 'master' into wandwor
[yosys.git] / passes / opt / opt_reduce.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-10-14 Clifford WolfRevert 90be0d8 as it causes endless loops for some...
2017-10-12 Clifford WolfMerge pull request #434 from Kmanfi/vector_fix
2017-10-12 Kaj TuomiFix input vector for reduce cells.
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-03 Clifford WolfUsing design->selected_modules() in opt_*
2014-12-28 Clifford Wolfusing dict and pool in opt_reduce
2014-10-31 Clifford WolfAdded "opt -full" alias for all more aggressive optimiz...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-02 Clifford WolfFixed a performance bug in opt_reduce
2014-08-01 Clifford WolfReplaced sha1 implementation
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-25 Clifford WolfFixed memory corruption in "opt_reduce" pass
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfAdded "opt_const -fine" and "opt_reduce -fine"
2014-07-18 Clifford WolfApply opt_reduce WR_EN opts to the whole mux tree drivi...
2014-07-17 Clifford WolfImproved opt_reduce handling of mem wr_en mux bits
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford Wolfimproved opt_reduce for $mem/$memwr WR_EN multiplexers
2014-05-12 Clifford WolfFixed bug in opt_reduce (see vloghammer issue_044)
2014-03-06 Clifford WolfFixed undef handling in opt_reduce
2013-11-10 Clifford WolfCleanups and bugfixes in response to new internal cell...
2013-03-01 Clifford WolfAdded help messages for opt_* passes
2013-02-27 Clifford WolfMoved stand-alone libs to libs/ directory and added...
2013-01-05 Clifford Wolfinitial import