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Add "wreduce -keepdc", fixes #1016
[yosys.git]
/
passes
/
opt
/
opt_reduce.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2017-10-14
Clifford Wolf
Revert 90be0d8 as it causes endless loops for some...
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2017-10-12
Clifford Wolf
Merge pull request #434 from Kmanfi/vector_fix
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2017-10-12
Kaj Tuomi
Fix input vector for reduce cells.
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-03
Clifford Wolf
Using design->selected_modules() in opt_*
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2014-12-28
Clifford Wolf
using dict and pool in opt_reduce
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2014-10-31
Clifford Wolf
Added "opt -full" alias for all more aggressive optimiz...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-30
Clifford Wolf
Added design->scratchpad
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-08-02
Clifford Wolf
Fixed a performance bug in opt_reduce
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2014-08-01
Clifford Wolf
Replaced sha1 implementation
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-25
Clifford Wolf
Fixed memory corruption in "opt_reduce" pass
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::expand() method
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-07-21
Clifford Wolf
Added "opt_const -fine" and "opt_reduce -fine"
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2014-07-18
Clifford Wolf
Apply opt_reduce WR_EN opts to the whole mux tree drivi...
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2014-07-17
Clifford Wolf
Improved opt_reduce handling of mem wr_en mux bits
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2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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2014-07-16
Clifford Wolf
improved opt_reduce for $mem/$memwr WR_EN multiplexers
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2014-05-12
Clifford Wolf
Fixed bug in opt_reduce (see vloghammer issue_044)
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2014-03-06
Clifford Wolf
Fixed undef handling in opt_reduce
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2013-11-10
Clifford Wolf
Cleanups and bugfixes in response to new internal cell...
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2013-03-01
Clifford Wolf
Added help messages for opt_* passes
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2013-02-27
Clifford Wolf
Moved stand-alone libs to libs/ directory and added...
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2013-01-05
Clifford Wolf
initial import
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