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Output pattern matcher items as log_debug()
[yosys.git]
/
passes
/
pmgen
/
xilinx_srl.cc
2019-09-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-30
Eddie Hung
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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2019-08-30
Eddie Hung
Merge pull request #1310 from SergeyDegtyar/master
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2019-08-30
Eddie Hung
Merge pull request #1321 from YosysHQ/eddie/xilinx_srl
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2019-08-30
Eddie Hung
Merge branch 'eddie/xilinx_srl' into xaig_arrival
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Cleanup
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-28
Eddie Hung
Merge branch 'eddie/xilinx_srl' into xaig_arrival
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2019-08-28
Eddie Hung
No need to replace Q of slice since $shiftx is autoremove-d
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2019-08-28
Eddie Hung
More cleanup
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2019-08-28
Eddie Hung
Do not use default_params dict, hardcode default values...
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-27
Eddie Hung
Missing close bracket
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2019-08-27
Eddie Hung
Remove leftover header
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2019-08-26
Eddie Hung
Merge branch 'master' into eddie/xilinx_srl
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2019-08-24
Eddie Hung
Create new $__XILINX_SHREG_ cell for variable length too
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2019-08-24
Eddie Hung
Create new cell for fixed length SRL
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2019-08-23
Eddie Hung
Fix last_cell.D
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2019-08-23
Eddie Hung
Update doc
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2019-08-23
Eddie Hung
Remove (* init *) entry when consumed into SRL
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2019-08-23
Eddie Hung
Forgot to slice
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2019-08-23
Eddie Hung
xilinx_srl to use 'slice' features of pmgen for word...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgen...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Add doc
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2019-08-22
Eddie Hung
Add copyright
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2019-08-22
Eddie Hung
Remove output_bits
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2019-08-22
Eddie Hung
Forgot to set ud_variable.minlen
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2019-08-22
Eddie Hung
Do not run xilinx_srl_pm in fixed loop
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Add comment
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2019-08-22
Eddie Hung
Add variable length support to xilinx_srl
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2019-08-21
Eddie Hung
Rename pattern to fixed
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2019-08-21
Eddie Hung
xilinx_srl to support FDRE and FDRE_1
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2019-08-21
Eddie Hung
Fix polarity of EN_POL
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2019-08-21
Eddie Hung
Add CLKPOL == 0
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2019-08-21
Eddie Hung
Reject if not minlen from inside pattern matcher
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2019-08-21
Eddie Hung
Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
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2019-08-21
Eddie Hung
Add init support
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2019-08-21
Eddie Hung
Fix spacing
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2019-08-21
Eddie Hung
Initial progress on xilinx_srl
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