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Remove (* init *) entry when consumed into SRL
[yosys.git]
/
passes
/
pmgen
/
xilinx_srl.cc
2019-08-23
Eddie Hung
Remove (* init *) entry when consumed into SRL
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2019-08-23
Eddie Hung
Forgot to slice
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2019-08-23
Eddie Hung
xilinx_srl to use 'slice' features of pmgen for word...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgen...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Add doc
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2019-08-22
Eddie Hung
Add copyright
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2019-08-22
Eddie Hung
Remove output_bits
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2019-08-22
Eddie Hung
Forgot to set ud_variable.minlen
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2019-08-22
Eddie Hung
Do not run xilinx_srl_pm in fixed loop
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Add comment
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2019-08-22
Eddie Hung
Add variable length support to xilinx_srl
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2019-08-21
Eddie Hung
Rename pattern to fixed
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2019-08-21
Eddie Hung
xilinx_srl to support FDRE and FDRE_1
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2019-08-21
Eddie Hung
Fix polarity of EN_POL
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2019-08-21
Eddie Hung
Add CLKPOL == 0
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2019-08-21
Eddie Hung
Reject if not minlen from inside pattern matcher
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2019-08-21
Eddie Hung
Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
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2019-08-21
Eddie Hung
Add init support
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2019-08-21
Eddie Hung
Fix spacing
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2019-08-21
Eddie Hung
Initial progress on xilinx_srl
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