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Merge remote-tracking branch 'origin/master' into xc7dsp
[yosys.git]
/
passes
/
pmgen
/
xilinx_srl.pmg
2019-09-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-20
Eddie Hung
Use new port/param overload in pmg
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2019-09-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-30
Eddie Hung
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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2019-08-30
Eddie Hung
Merge pull request #1310 from SergeyDegtyar/master
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2019-08-30
Eddie Hung
Merge pull request #1321 from YosysHQ/eddie/xilinx_srl
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-28
Eddie Hung
Account for D port being a constant
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2019-08-28
Eddie Hung
Account for D port being a constant
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2019-08-28
Eddie Hung
Merge branch 'eddie/xilinx_srl' into xaig_arrival
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2019-08-28
Eddie Hung
More cleanup
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2019-08-28
Eddie Hung
Do not use default_params dict, hardcode default values...
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2019-08-28
Eddie Hung
Always generate if no match
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-27
Eddie Hung
Improve xilinx_srl.fixed generate, add .variable generate
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2019-08-26
Eddie Hung
Populate generate for xilinx_srl.fixed pattern
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2019-08-26
Eddie Hung
Merge branch 'master' into eddie/xilinx_srl
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2019-08-24
Eddie Hung
Do not allow Q of last cell of variable length SRL...
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2019-08-24
Eddie Hung
Also add first.Q to chain_bits since variable length
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2019-08-24
Eddie Hung
Do not enforce !EN_POLARITY on $dffe
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2019-08-24
Eddie Hung
Cleanup FDRE matching
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2019-08-23
Eddie Hung
Oops don't need a finally block
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2019-08-23
Eddie Hung
Keep track of bits in variable length chain, to check...
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2019-08-23
Eddie Hung
Don't forget $dff has no EN
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2019-08-23
Eddie Hung
Same for variable length
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2019-08-23
Eddie Hung
Filter on en_port for fixed length
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2019-08-23
Eddie Hung
Check clock is consistent
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2019-08-23
Eddie Hung
Check for non unique nusers/fanouts
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2019-08-23
Eddie Hung
Cope with possibility that D could connect to Q on...
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2019-08-23
Eddie Hung
xilinx_srl to use 'slice' features of pmgen for word...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgen...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Remove output_bits
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Reuse var
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2019-08-22
Eddie Hung
Revert "Trim shiftx_width when upper bits are 1'bx"
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2019-08-22
Eddie Hung
Trim shiftx_width when upper bits are 1'bx
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2019-08-22
Eddie Hung
Add variable length support to xilinx_srl
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2019-08-21
Eddie Hung
Rename pattern to fixed
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2019-08-21
Eddie Hung
attribute -> attr
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2019-08-21
Eddie Hung
Use Cell::has_keep_attribute()
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2019-08-21
Eddie Hung
xilinx_srl to support FDRE and FDRE_1
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2019-08-21
Eddie Hung
Reject if not minlen from inside pattern matcher
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2019-08-21
Eddie Hung
Get wire via SigBit
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2019-08-21
Eddie Hung
Respect \keep on cells or wires
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2019-08-21
Eddie Hung
Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
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2019-08-21
Eddie Hung
Initial progress on xilinx_srl
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