Merge remote-tracking branch 'origin/master' into xc7dsp
[yosys.git] / passes / pmgen / xilinx_srl.pmg
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungUse new port/param overload in pmg
2019-09-03 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 Eddie HungMerge pull request #1340 from YosysHQ/eddie/abc_no_clean
2019-08-30 Eddie HungMerge pull request #1310 from SergeyDegtyar/master
2019-08-30 Eddie HungMerge pull request #1321 from YosysHQ/eddie/xilinx_srl
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-28 Eddie HungAccount for D port being a constant
2019-08-28 Eddie HungAccount for D port being a constant
2019-08-28 Eddie HungMerge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 Eddie HungMore cleanup
2019-08-28 Eddie HungDo not use default_params dict, hardcode default values...
2019-08-28 Eddie HungAlways generate if no match
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-27 Eddie HungImprove xilinx_srl.fixed generate, add .variable generate
2019-08-26 Eddie HungPopulate generate for xilinx_srl.fixed pattern
2019-08-26 Eddie HungMerge branch 'master' into eddie/xilinx_srl
2019-08-24 Eddie HungDo not allow Q of last cell of variable length SRL...
2019-08-24 Eddie HungAlso add first.Q to chain_bits since variable length
2019-08-24 Eddie HungDo not enforce !EN_POLARITY on $dffe
2019-08-24 Eddie HungCleanup FDRE matching
2019-08-23 Eddie HungOops don't need a finally block
2019-08-23 Eddie HungKeep track of bits in variable length chain, to check...
2019-08-23 Eddie HungDon't forget $dff has no EN
2019-08-23 Eddie HungSame for variable length
2019-08-23 Eddie HungFilter on en_port for fixed length
2019-08-23 Eddie HungCheck clock is consistent
2019-08-23 Eddie HungCheck for non unique nusers/fanouts
2019-08-23 Eddie HungCope with possibility that D could connect to Q on...
2019-08-23 Eddie Hungxilinx_srl to use 'slice' features of pmgen for word...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgen...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungRemove output_bits
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungReuse var
2019-08-22 Eddie HungRevert "Trim shiftx_width when upper bits are 1'bx"
2019-08-22 Eddie HungTrim shiftx_width when upper bits are 1'bx
2019-08-22 Eddie HungAdd variable length support to xilinx_srl
2019-08-21 Eddie HungRename pattern to fixed
2019-08-21 Eddie Hungattribute -> attr
2019-08-21 Eddie HungUse Cell::has_keep_attribute()
2019-08-21 Eddie Hungxilinx_srl to support FDRE and FDRE_1
2019-08-21 Eddie HungReject if not minlen from inside pattern matcher
2019-08-21 Eddie HungGet wire via SigBit
2019-08-21 Eddie HungRespect \keep on cells or wires
2019-08-21 Eddie HungMerge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
2019-08-21 Eddie HungInitial progress on xilinx_srl