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Update example for GW1NR-9
[yosys.git] / passes / pmgen /
2019-09-02 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-09-01 Eddie HungMerge pull request #1344 from YosysHQ/eddie/ice40_signe... tree | commitdiff
2019-08-30 Eddie HungMissing dep for test_pmgen tree | commitdiff
2019-08-30 Eddie HungMerge pull request #1340 from YosysHQ/eddie/abc_no_clean tree | commitdiff
2019-08-30 Eddie HungDo not restrict multiplier to unsigned tree | commitdiff
2019-08-30 Eddie HungMerge pull request #1310 from SergeyDegtyar/master tree | commitdiff
2019-08-30 Eddie HungMerge pull request #1321 from YosysHQ/eddie/xilinx_srl tree | commitdiff
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-29 SergeyMerge pull request #3 from YosysHQ/Sergey/tests_ice40 tree | commitdiff
2019-08-29 Eddie HungCleanup tree | commitdiff
2019-08-28 Eddie HungAccount for D port being a constant tree | commitdiff
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/clifford/async2syn... tree | commitdiff
2019-08-28 Eddie HungNo need to replace Q of slice since $shiftx is autoremove-d tree | commitdiff
2019-08-28 Eddie HungMore cleanup tree | commitdiff
2019-08-28 Eddie HungMore cleanup tree | commitdiff
2019-08-28 Eddie HungDo not use default_params dict, hardcode default values... tree | commitdiff
2019-08-28 Eddie HungAlways generate if no match tree | commitdiff
2019-08-28 Eddie HungRename test_pmgen arg xilinx_srl.{fixed,variable} tree | commitdiff
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-27 Clifford WolfMerge pull request #1325 from YosysHQ/eddie/sat_init tree | commitdiff
2019-08-27 Eddie HungMissing close bracket tree | commitdiff
2019-08-27 Eddie HungRemove leftover header tree | commitdiff
2019-08-27 Eddie HungImprove xilinx_srl.fixed generate, add .variable generate tree | commitdiff
2019-08-27 Eddie HungAccount for maxsubcnt overflowing tree | commitdiff
2019-08-27 Eddie HungAdd xilinx_srl_pm.variable to test_pmgen tree | commitdiff
2019-08-26 Eddie HungPopulate generate for xilinx_srl.fixed pattern tree | commitdiff
2019-08-26 Eddie HungAdd xilinx_srl_fixed, fix typos tree | commitdiff
2019-08-26 Eddie HungMerge branch 'master' into eddie/xilinx_srl tree | commitdiff
2019-08-26 Eddie HungMerge branch 'master' into mwk/xilinx_bufgmap tree | commitdiff
2019-08-26 Clifford WolfMerge tag 'yosys-0.9' tree | commitdiff
2019-08-25 Clifford WolfMerge pull request #1112 from acw1251/pyosys_sigsig_issue tree | commitdiff
2019-08-24 Clifford WolfMerge pull request #1327 from YosysHQ/clifford/pmgen tree | commitdiff
2019-08-24 Eddie HungCreate new $__XILINX_SHREG_ cell for variable length too tree | commitdiff
2019-08-24 Eddie HungDo not allow Q of last cell of variable length SRL... tree | commitdiff
2019-08-24 Eddie HungAlso add first.Q to chain_bits since variable length tree | commitdiff
2019-08-24 Eddie HungDo not enforce !EN_POLARITY on $dffe tree | commitdiff
2019-08-24 Eddie HungCreate new cell for fixed length SRL tree | commitdiff
2019-08-24 Eddie HungCleanup FDRE matching tree | commitdiff
2019-08-23 Eddie HungOops don't need a finally block tree | commitdiff
2019-08-23 Eddie HungKeep track of bits in variable length chain, to check... tree | commitdiff
2019-08-23 Eddie HungDon't forget $dff has no EN tree | commitdiff
2019-08-23 Eddie HungSame for variable length tree | commitdiff
2019-08-23 Eddie HungFilter on en_port for fixed length tree | commitdiff
2019-08-23 Eddie HungCheck clock is consistent tree | commitdiff
2019-08-23 Eddie HungFix last_cell.D tree | commitdiff
2019-08-23 Eddie HungRevert "Add a unique argument to pmgen's nusers()" tree | commitdiff
2019-08-23 Eddie HungRevert "Fix polarity" tree | commitdiff
2019-08-23 Eddie HungFix polarity tree | commitdiff
2019-08-23 Eddie HungCheck for non unique nusers/fanouts tree | commitdiff
2019-08-23 Eddie HungAdd a unique argument to pmgen's nusers() tree | commitdiff
2019-08-23 Eddie HungUpdate doc tree | commitdiff
2019-08-23 Eddie HungRemove (* init *) entry when consumed into SRL tree | commitdiff
2019-08-23 Eddie Hungindo -> into tree | commitdiff
2019-08-23 Eddie Hungindo -> into tree | commitdiff
2019-08-23 Eddie HungForgot to slice tree | commitdiff
2019-08-23 Eddie HungCope with possibility that D could connect to Q on... tree | commitdiff
2019-08-23 Eddie Hungxilinx_srl to use 'slice' features of pmgen for word... tree | commitdiff
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgen... tree | commitdiff
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into mwk... tree | commitdiff
2019-08-23 Clifford WolfFix port hanlding in pmgen tree | commitdiff
2019-08-23 Clifford WolfAdd pmgen slices and choices tree | commitdiff
2019-08-22 Eddie HungAdd doc tree | commitdiff
2019-08-22 Eddie HungAdd copyright tree | commitdiff
2019-08-22 Eddie Hungpmgen to also iterate over all module ports tree | commitdiff
2019-08-22 Eddie HungRemove output_bits tree | commitdiff
2019-08-22 Eddie HungForgot to set ud_variable.minlen tree | commitdiff
2019-08-22 Eddie HungDo not run xilinx_srl_pm in fixed loop tree | commitdiff
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-22 Eddie HungMerge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx tree | commitdiff
2019-08-22 Clifford WolfMerge pull request #1289 from mmicko/anlogic_fixes tree | commitdiff
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix tree | commitdiff
2019-08-22 Clifford WolfMerge pull request #1316 from YosysHQ/eddie/fix_mem2reg tree | commitdiff
2019-08-22 Eddie HungReuse var tree | commitdiff
2019-08-22 Eddie HungRevert "Trim shiftx_width when upper bits are 1'bx" tree | commitdiff
2019-08-22 Eddie HungTrim shiftx_width when upper bits are 1'bx tree | commitdiff
2019-08-22 Eddie HungAdd comment tree | commitdiff
2019-08-22 Eddie HungAdd variable length support to xilinx_srl tree | commitdiff
2019-08-21 Eddie HungRename pattern to fixed tree | commitdiff
2019-08-21 Eddie Hungattribute -> attr tree | commitdiff
2019-08-21 Eddie HungUse Cell::has_keep_attribute() tree | commitdiff
2019-08-21 Eddie Hungxilinx_srl to support FDRE and FDRE_1 tree | commitdiff
2019-08-21 Eddie HungFix polarity of EN_POL tree | commitdiff
2019-08-21 whitequarkMerge pull request #1315 from mmicko/fix_dependencies tree | commitdiff
2019-08-21 Eddie HungAdd CLKPOL == 0 tree | commitdiff
2019-08-21 Eddie HungReject if not minlen from inside pattern matcher tree | commitdiff
2019-08-21 Eddie HungGet wire via SigBit tree | commitdiff
2019-08-21 Eddie HungRespect \keep on cells or wires tree | commitdiff
2019-08-21 Eddie HungMerge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl tree | commitdiff
2019-08-21 Eddie HungAdd init support tree | commitdiff
2019-08-21 Eddie HungFix spacing tree | commitdiff
2019-08-21 Eddie HungInitial progress on xilinx_srl tree | commitdiff
2019-08-21 Miodrag MilanovicFix test_pmgen deps tree | commitdiff
2019-08-21 Clifford WolfMerge pull request #1314 from YosysHQ/eddie/fix_techmap tree | commitdiff
2019-08-21 Eddie HungFix copy-paste typo tree | commitdiff
2019-08-20 Eddie HungMerge pull request #1209 from YosysHQ/eddie/synth_xilinx tree | commitdiff
2019-08-20 Eddie HungMerge pull request #1304 from YosysHQ/eddie/abc9_refactor tree | commitdiff
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-08-20 Clifford WolfMerge pull request #1298 from YosysHQ/clifford/pmgen tree | commitdiff
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