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Merge branch 'master' into wandwor
[yosys.git]
/
passes
/
proc
/
proc_arst.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-09
Clifford Wolf
Minor fixes in handling of "init" attribute
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-01-01
Clifford Wolf
Removed SigSpec::extend_xx() api
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2014-12-24
Clifford Wolf
Renamed extend() to extend_xx(), changed most users...
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-27
Clifford Wolf
Using new obj iterator API in a few places
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-23
Clifford Wolf
Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-02-21
Clifford Wolf
Added workaround for vhdl-style edge triggers from...
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2013-12-27
Clifford Wolf
Added support for non-const === and !== (for miter...
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2013-11-20
Clifford Wolf
Added "proc_arst -global_arst" feature
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2013-10-18
Clifford Wolf
Added handling of multiple async paths in proc_arst
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2013-03-25
Clifford Wolf
Added nosync attribute and some async reset related...
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2013-03-01
Clifford Wolf
Added help messages to proc_* passes
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2013-01-05
Clifford Wolf
initial import
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