Merge branch 'master' into wandwor
[yosys.git] / passes / proc / proc_arst.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-09 Clifford WolfMinor fixes in handling of "init" attribute
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-01-01 Clifford WolfRemoved SigSpec::extend_xx() api
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users...
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-21 Clifford WolfAdded workaround for vhdl-style edge triggers from...
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2013-12-27 Clifford WolfAdded support for non-const === and !== (for miter...
2013-11-20 Clifford WolfAdded "proc_arst -global_arst" feature
2013-10-18 Clifford WolfAdded handling of multiple async paths in proc_arst
2013-03-25 Clifford WolfAdded nosync attribute and some async reset related...
2013-03-01 Clifford WolfAdded help messages to proc_* passes
2013-01-05 Clifford Wolfinitial import