Merge branch 'master' into map_cells_before_map_luts
[yosys.git] / passes / proc / proc_dff.cc
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-13 Clifford WolfMerge pull request #468 from grahamedgecombe/fix-sb...
2017-12-12 Clifford WolfAdd warnings for driver-driver conflicts between FFs...
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-11-09 Clifford WolfAdded log_warning() API
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfReplaced depricated NEW_WIRE macro with module->addWire...
2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-10-18 Clifford WolfAdded dffsr support to proc_dff pass
2013-03-18 Clifford WolfMerge branch 'hansi'
2013-03-18 Johann Glaserfixed typos
2013-03-01 Clifford WolfAdded help messages to proc_* passes
2013-01-05 Clifford Wolfinitial import