Refactoring: Renamed RTLIL::Module::cells to cells_
[yosys.git] / passes / proc / proc_dff.cc
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfReplaced depricated NEW_WIRE macro with module->addWire...
2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-10-18 Clifford WolfAdded dffsr support to proc_dff pass
2013-03-18 Clifford WolfMerge branch 'hansi'
2013-03-18 Johann Glaserfixed typos
2013-03-01 Clifford WolfAdded help messages to proc_* passes
2013-01-05 Clifford Wolfinitial import