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Refactoring: Renamed RTLIL::Module::cells to cells_
[yosys.git]
/
passes
/
proc
/
proc_dff.cc
2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-07-21
Clifford Wolf
Replaced depricated NEW_WIRE macro with module->addWire...
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2014-06-19
Clifford Wolf
Do not create $dffsr cells with no-op resets in proc_dff
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2013-10-24
Clifford Wolf
Added support for complex set-reset flip-flops in proc_dff
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2013-10-21
Clifford Wolf
Improved handling of dff with async resets
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2013-10-18
Clifford Wolf
Added dffsr support to proc_dff pass
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2013-03-18
Clifford Wolf
Merge branch 'hansi'
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2013-03-18
Johann Glaser
fixed typos
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2013-03-01
Clifford Wolf
Added help messages to proc_* passes
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2013-01-05
Clifford Wolf
initial import
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