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Fix "tee" handling of log_streams
[yosys.git]
/
passes
/
proc
/
proc_mux.cc
2019-04-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin' into xc7srl
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2019-04-20
Clifford Wolf
Merge pull request #942 from YosysHQ/clifford/fix931
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2019-04-18
Eddie Hung
Merge branch 'master' into eddie/fix_retime
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2019-04-18
Clifford Wolf
Improve proc full_case detection and handling, fixes...
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2019-04-16
Eddie Hung
Merge pull request #939 from YosysHQ/revert895
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2019-04-16
Eddie Hung
Revert #895
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2019-04-08
Eddie Hung
Merge branch 'undo_pr895' into xc7srl
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2019-04-08
Eddie Hung
Undo #895 by instead setting an attribute
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-03
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Sylvain Munaut
proc_mux: Fix crash when trying to optimize non-existan...
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-23
Eddie Hung
Add a pmux-to-shiftx optimisation to proc_mux
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-06
Clifford Wolf
Added "proc_mux -ifx"
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2016-04-25
Clifford Wolf
Fixed proc_mux performance bug
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-12-02
Clifford Wolf
Improved proc_mux performance for huge always blocks
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Using new obj iterator API in a few places
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-23
Clifford Wolf
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-22
Clifford Wolf
Fixed memory corruption with new SigSpec API in proc_mux
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-01-14
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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2014-01-03
Clifford Wolf
Tiny cleanup in proc_mux.cc
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (passes)
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2013-03-01
Clifford Wolf
Added help messages to proc_* passes
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2013-01-05
Clifford Wolf
initial import
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