Added "proc_dlatch"
[yosys.git] / passes / proc /
2015-02-12 Clifford WolfAdded "proc_dlatch"
2015-01-01 Clifford WolfRemoved SigSpec::extend_xx() api
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users...
2014-11-09 Clifford WolfAdded log_warning() API
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-12 Clifford WolfFixed handling of constant-true branches in proc_clean
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfFixed memory corruption with new SigSpec API in proc_mux
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfReplaced depricated NEW_WIRE macro with module->addWire...
2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff
2014-02-21 Clifford WolfAdded workaround for vhdl-style edge triggers from...
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-03 Clifford WolfTiny cleanup in proc_mux.cc
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2013-12-27 Clifford WolfAdded support for non-const === and !== (for miter...
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync...
2013-11-20 Clifford WolfAdded "proc_arst -global_arst" feature
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-24 Clifford WolfFixed handling of boolean attributes (passes)
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-10-18 Clifford WolfAdded handling of multiple async paths in proc_arst
2013-10-18 Clifford WolfAdded dffsr support to proc_dff pass
2013-03-25 Clifford WolfAdded nosync attribute and some async reset related...
2013-03-18 Clifford WolfMerge branch 'hansi'
2013-03-18 Johann Glaserfixed typos
2013-03-01 Clifford WolfAdded help messages to proc_* passes
2013-01-05 Clifford Wolfinitial import