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Merge remote-tracking branch 'upstream/master'
[yosys.git]
/
passes
/
sat
/
eval.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-25
Clifford Wolf
Import more std:: stuff into Yosys namespace
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-21
Clifford Wolf
Replaced ezDefaultSAT with ezSatPtr
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2014-11-09
Clifford Wolf
Added log_warning() API
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2014-10-10
Clifford Wolf
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because...
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::expand() method
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2014-07-23
Clifford Wolf
Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23
Clifford Wolf
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-02-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-06
Clifford Wolf
Added generic RTLIL::SigSpec::parse_sel() with support...
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Major rewrite of "freduce" command
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2013-12-07
Clifford Wolf
Fixed compiler warining in passes/sat/eval.cc
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2013-12-07
Clifford Wolf
Added eval -set-undef and eval -table
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2013-11-25
Clifford Wolf
Improvements in satgen undef handling
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2013-11-25
Clifford Wolf
Improvements in satgen undef handling
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2013-11-25
Clifford Wolf
Started implementing undef handling in satgen
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2013-11-09
Clifford Wolf
Improved user-friendliness of "sat" and "eval" expressi...
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2013-11-09
Clifford Wolf
Added verification of SAT model to "eval -vloghammer_re...
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2013-11-06
Clifford Wolf
Added handling of unconnected/unspecified signals to...
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2013-11-06
Clifford Wolf
Added correct RTL undef handling to eval vloghammer...
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2013-11-06
Clifford Wolf
Added eval -vloghammer_report mode
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2013-08-15
Clifford Wolf
Added eval -brute_force_equiv_checker_x mode
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2013-06-19
Clifford Wolf
Added "eval" pass
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