Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git] / passes / sat / eval.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-21 Clifford WolfReplaced ezDefaultSAT with ezSatPtr
2014-11-09 Clifford WolfAdded log_warning() API
2014-10-10 Clifford WolfRenamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because...
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-06 Clifford WolfAdded generic RTLIL::SigSpec::parse_sel() with support...
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfMajor rewrite of "freduce" command
2013-12-07 Clifford WolfFixed compiler warining in passes/sat/eval.cc
2013-12-07 Clifford WolfAdded eval -set-undef and eval -table
2013-11-25 Clifford WolfImprovements in satgen undef handling
2013-11-25 Clifford WolfImprovements in satgen undef handling
2013-11-25 Clifford WolfStarted implementing undef handling in satgen
2013-11-09 Clifford WolfImproved user-friendliness of "sat" and "eval" expressi...
2013-11-09 Clifford WolfAdded verification of SAT model to "eval -vloghammer_re...
2013-11-06 Clifford WolfAdded handling of unconnected/unspecified signals to...
2013-11-06 Clifford WolfAdded correct RTL undef handling to eval vloghammer...
2013-11-06 Clifford WolfAdded eval -vloghammer_report mode
2013-08-15 Clifford WolfAdded eval -brute_force_equiv_checker_x mode
2013-06-19 Clifford WolfAdded "eval" pass