Merge pull request #1050 from YosysHQ/clifford/wandwor
[yosys.git] / passes / sat / freduce.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-05-28 Clifford WolfAdd "setundef -anyseq"
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-30 Clifford WolfAdded logic-loop error handling to freduce
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-21 Clifford WolfReplaced ezDefaultSAT with ezSatPtr
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfRemoved deprecated module->new_wire()
2014-03-07 Clifford WolfFixed bug in freduce command
2014-03-07 Clifford WolfSome minor code cleanups in freduce command
2014-03-06 Clifford WolfAdded freduce -dump
2014-03-06 Clifford WolfAdded freduce -stop
2014-03-03 Clifford Wolffixed freduce for Minisat::SimpSolver: use frozen_literal()
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-04 Clifford WolfImproved performance of freduce input cone reduction
2014-01-03 Clifford WolfImproved freduce performance on const signals
2014-01-03 Clifford WolfPerformance improvements in freduce pass
2014-01-03 Clifford WolfMore freduce cleanups
2014-01-03 Clifford WolfCleanups in freduce command
2014-01-03 Ahmed Irfansplitnet -driver feature
2014-01-03 Clifford WolfUse selection in freduce command
2014-01-03 Clifford WolfAnother small freduce cleanup/bugfix
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-03 Clifford WolfMore freduce cleanups and bugfixes
2014-01-02 Clifford WolfFixed more complex undef cases in freduce
2014-01-02 Clifford WolfMore "freduce" related fixes and improvements
2014-01-02 Clifford WolfSome cleanups in freduce -inv mode (and switched from...
2014-01-02 Clifford WolfMajor rewrite of "freduce" command
2013-08-10 Clifford Wolffreduce performance fix
2013-08-08 Clifford WolfAdded -try option to freduce pass
2013-08-07 Clifford WolfFixed topological ordering in freduce pass
2013-08-06 Clifford WolfSmall bugfixes in freduce pass
2013-08-06 Clifford WolfAdded freduce command