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Error out if no top module given before 'sim'
[yosys.git]
/
passes
/
sat
/
sim.cc
2019-06-05
Eddie Hung
Error out if no top module given before 'sim'
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
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2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-09-17
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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2018-09-14
Clifford Wolf
Merge pull request #627 from acw1251/master
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2018-09-12
acw1251
Fixed minor typo in "sim" help message
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2017-08-20
Clifford Wolf
Rename "singleton" pass to "uniquify"
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2017-08-18
Clifford Wolf
Add "sim -zinit -rstlen"
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2017-08-18
Clifford Wolf
Merge branch 'sim'
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2017-08-18
Clifford Wolf
Add "sim" support for memories
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2017-08-18
Clifford Wolf
Add support for assert/assume/cover to "sim" command
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2017-08-17
Clifford Wolf
Add writeback mode to "sim" command
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2017-08-17
Clifford Wolf
Improve "sim" command
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2017-08-16
Clifford Wolf
Add "sim" command skeleton
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