Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023
[yosys.git] / passes / sat /
2017-05-28 Clifford WolfAdd "setundef -anyseq"
2016-10-19 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-10-17 Clifford WolfBugfix in "miter -assert" handling of assumptions
2016-10-17 Clifford WolfAdded clk2fflogic support for $dffsr and $dlatch
2016-10-16 Clifford WolfImprovements and bugfixes in clk2fflogic
2016-10-14 Clifford WolfSome minor build fixes for Visual C
2016-10-14 Clifford WolfAdded clk2fflogic
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-09-07 Clifford WolfImprovements in assertpmux
2016-09-06 Clifford WolfAdded assertpmux
2016-09-06 Clifford WolfRun log_flush() before solving in sat command
2016-07-24 Clifford WolfMoved SatHelper::setup_init() code to SatHelper::setup()
2016-07-23 Clifford WolfAdded $initstate support to "sat" command
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-04-07 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-05 Clifford WolfImproved formatting of "sat" output tables
2016-04-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-03-31 Clifford WolfRenamed opt_const to opt_expr
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-10-24 Clifford Wolfrenamed SigSpec::to_single_sigbit() to SigSpec::as_bit...
2015-08-18 Clifford WolfAdded sat -show-regs, -show-public, -show-all
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-25 Clifford WolfAdded "miter -assert"
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-30 Clifford WolfAdded logic-loop error handling to freduce
2015-04-18 Clifford Wolfdon't consider blackbox modules in "sat" command
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-22 Clifford WolfFixed "sat -initsteps" off-by-one bug
2015-02-21 Clifford WolfAdded "sat -stepsize" and "sat -tempinduct-step"
2015-02-21 Clifford Wolfsat docu change
2015-02-21 Clifford WolfWhen "sat -tempinduct-baseonly -maxsteps N" reaches...
2015-02-21 Clifford WolfAdded "sat -tempinduct-baseonly -tempinduct-inductonly"
2015-02-21 Clifford WolfFixed basecase init for "sat -tempinduct"
2015-02-21 Clifford WolfReplaced ezDefaultSAT with ezSatPtr
2015-02-19 Clifford Wolfformat fixes in "sat -dump_json"
2015-02-19 Clifford WolfAdded "sat -dump_json" (WaveJSON format)
2015-01-27 Clifford WolfImproved an error message
2015-01-27 Clifford WolfAdded "sat -show-ports"
2015-01-22 Clifford WolfMoved equiv stuff to passes/equiv/
2015-01-21 Clifford WolfProgress in equiv_simple
2015-01-19 Clifford WolfAdded equiv_simple
2015-01-19 Clifford WolfAdded equiv_status
2015-01-19 Clifford WolfAdded equiv_make command
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users...
2014-11-09 Clifford WolfAdded log_warning() API
2014-10-10 Clifford WolfRenamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because...
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-09-01 Clifford WolfFixes in old SAT example.ys
2014-09-01 Clifford WolfMoved "share" and "wreduce" to passes/opt/
2014-08-24 Clifford Wolfazonenberg: Make dump_vcd save model when temporal...
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-09 Clifford WolfFixed "share" for complex scenarios with never-active...
2014-08-09 Clifford WolfDo not share any $reduce_* cells (its complicated and...
2014-08-08 Clifford WolfFixed sharing of reduce operator
2014-08-08 Clifford WolfAdded "sat -prove-skip"
2014-08-07 Clifford WolfUse "-keepdc" in "miter -equiv -flatten"
2014-08-03 Clifford WolfFixed "share" for memory read ports
2014-08-02 Clifford WolfRemoved at() method from RTLIL::IdString
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed modwalker.h to modtools.h
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname)
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfRemoved deprecated module->new_wire()
2014-07-21 Clifford WolfWider range of cell types supported in "share" pass
2014-07-21 Clifford WolfUse ezSAT::non_incremental() in "share" pass
2014-07-20 Clifford WolfAdded support for resource sharing in mux control logic
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