abc9_ops: still emit delay table even box has no timing
[yosys.git] / passes / techmap / extract.cc
2020-01-29 Claire WolfMerge branch 'vector_fix' of https://github.com/Kmanfi...
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-08-30 David ShahMerge branch 'master' into xc7dsp
2019-08-26 Clifford WolfMerge tag 'yosys-0.9'
2019-08-25 Clifford WolfMerge pull request #1112 from acw1251/pyosys_sigsig_issue
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-19 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-08-18 Miodrag MilanovicMerge remote-tracking branch 'upstream/master' into...
2019-08-18 whitequarkMerge branch 'master' into eddie/pr1266_again
2019-08-17 Clifford WolfMerge pull request #1283 from YosysHQ/clifford/fix1255
2019-08-16 Eddie HungMerge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 Eddie HungMerge pull request #1250 from bwidawsk/master
2019-08-16 Eddie HungMerge https://github.com/bogdanvuk/yosys into bogdanvuk...
2019-08-16 Eddie HungMerge remote-tracking branch 'origin/master' into mwk...
2019-08-15 Clifford WolfMerge pull request #1299 from YosysHQ/eddie/cleanup2
2019-08-15 Eddie HungID(\\.*) -> ID(.*)
2019-08-15 Eddie HungTransform all "\\*" identifiers into ID()
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 Serge BazanskiMerge pull request #1152 from 1138-4EB/feat-docker
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-10 Clifford WolfMerge pull request #1258 from YosysHQ/eddie/cleanup
2019-08-07 Eddie Hungsubstr() -> compare()
2019-08-07 Eddie Hungstoi -> atoi
2019-08-06 Eddie HungUse std::stoi instead of atoi(<str>.c_str())
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-10-24 Clifford Wolfequiv_purge bugfix, using SigChunk in Yosys namespace
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-08 Clifford WolfAdded support for "file names with blanks"
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-10-10 Clifford WolfMore Win32 build fixes
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-14 Clifford WolfAdded module->ports
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-29 Clifford WolfAdded "techmap -map %{design-name}"
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-20 Clifford WolfAdded "extract -ignore_parameters" and "extract -ignore...
2014-02-20 Clifford WolfAdded "extract -map %<design_name>"
2014-02-08 Clifford WolfMoved some passes to other source directories