2019-03-28 |
Benedikt Tutzer | Merge remote-tracking branch 'origin/master' into featu... |
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2018-09-17 |
Udi Finkelstein | Merge branch 'master' into pr_reg_wire_error |
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2018-08-22 |
Jim Lawson | Merge pull request #1 from YosysHQ/master |
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2018-08-18 |
Aman Goel | Merge pull request #3 from YosysHQ/master |
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2018-08-15 |
Clifford Wolf | Merge pull request #573 from cr1901/msys-64 |
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2018-08-15 |
Clifford Wolf | Merge pull request #591 from hzeller/virtual-override |
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2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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2016-04-23 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2016-04-21 |
Clifford Wolf | Added "yosys -D" feature |
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2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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2015-10-25 |
Clifford Wolf | Import more std:: stuff into Yosys namespace |
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2015-10-24 |
Clifford Wolf | equiv_purge bugfix, using SigChunk in Yosys namespace |
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2015-08-14 |
Clifford Wolf | Re-created command-reference-manual.tex, copied some... |
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2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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2015-04-08 |
Clifford Wolf | Added support for "file names with blanks" |
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2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-10-10 |
Clifford Wolf | More Win32 build fixes |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-08-23 |
Clifford Wolf | Changed frontend-api from FILE to std::istream |
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2014-08-23 |
Clifford Wolf | Changed backend-api from FILE to std::ostream |
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2014-08-14 |
Clifford Wolf | Added module->ports |
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2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
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2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString |
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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2014-07-29 |
Clifford Wolf | Added "techmap -map %{design-name}" |
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2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
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2014-07-26 |
Clifford Wolf | Changed more code to the new RTLIL::Wire constructors |
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2014-07-26 |
Clifford Wolf | More RTLIL::Cell API usage cleanups |
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2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::expand() method |
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2014-07-23 |
Clifford Wolf | Fixed all users of SigSpec::chunks_rw() and removed it |
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2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
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2014-02-20 |
Clifford Wolf | Added "extract -ignore_parameters" and "extract -ignore... |
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2014-02-20 |
Clifford Wolf | Added "extract -map %<design_name>" |
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2014-02-08 |
Clifford Wolf | Moved some passes to other source directories |
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