add MUX support
[yosys.git] / passes /
2019-09-04 Pepijn de VosMerge remote-tracking branch 'diego/gowin'
2019-09-02 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-09-01 Eddie HungMerge pull request #1344 from YosysHQ/eddie/ice40_signe...
2019-09-01 Clifford WolfMerge pull request #1347 from mmicko/fix_select_error_msg
2019-09-01 Miodrag MilanovicFix select command error msg, fixes issue #1081
2019-08-30 Eddie HungMissing dep for test_pmgen
2019-08-30 Eddie HungMerge pull request #1340 from YosysHQ/eddie/abc_no_clean
2019-08-30 Eddie HungDo not restrict multiplier to unsigned
2019-08-30 Eddie HungMerge pull request #1310 from SergeyDegtyar/master
2019-08-30 Eddie HungMerge pull request #1321 from YosysHQ/eddie/xilinx_srl
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-30 Eddie HungMerge pull request #1337 from YosysHQ/eddie/fix_carry_w...
2019-08-30 Eddie HungOutput has priority over input when stitching in abc9
2019-08-29 Eddie Hungabc9 to not call "clean" at end of run (often called...
2019-08-29 SergeyMerge pull request #2 from YosysHQ/master
2019-08-29 SergeyMerge pull request #3 from YosysHQ/Sergey/tests_ice40
2019-08-29 Eddie HungFix typo that's gone unnoticed for 5 months!?!
2019-08-29 Eddie HungCleanup
2019-08-28 Eddie HungAccount for D port being a constant
2019-08-28 Eddie HungMerge pull request #1334 from YosysHQ/clifford/async2sy...
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/clifford/async2syn...
2019-08-28 Eddie HungNo need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 Eddie HungMore cleanup
2019-08-28 Eddie HungMore cleanup
2019-08-28 Eddie HungDo not use default_params dict, hardcode default values...
2019-08-28 Eddie HungAlways generate if no match
2019-08-28 Eddie HungRename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-28 David ShahMerge pull request #1332 from YosysHQ/dave/ecp5gsr
2019-08-28 Clifford WolfMerge pull request #1335 from YosysHQ/clifford/paramap
2019-08-28 Clifford WolfFix typo
2019-08-28 Clifford WolfAdd "paramap" pass
2019-08-28 Clifford WolfAdd $dlatch support to async2sync
2019-08-27 Clifford WolfMerge pull request #1325 from YosysHQ/eddie/sat_init
2019-08-27 Eddie HungMerge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
2019-08-27 Eddie HungIgnore all 1'bx in (* init *)
2019-08-27 Marcin Koƛcielnickiimprove clkbuf_inhibit propagation upwards through...
2019-08-27 Eddie HungMissing close bracket
2019-08-27 Eddie HungRevert "In sat: 'x' in init attr should not override...
2019-08-27 Eddie HungRemove leftover header
2019-08-27 Eddie HungImprove xilinx_srl.fixed generate, add .variable generate
2019-08-27 Eddie HungAccount for maxsubcnt overflowing
2019-08-27 Eddie HungAdd xilinx_srl_pm.variable to test_pmgen
2019-08-26 Eddie HungPopulate generate for xilinx_srl.fixed pattern
2019-08-26 Eddie HungAdd xilinx_srl_fixed, fix typos
2019-08-26 Eddie HungMerge branch 'master' into eddie/xilinx_srl
2019-08-26 Eddie HungMerge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 Clifford WolfMerge tag 'yosys-0.9'
2019-08-25 Clifford WolfMerge pull request #1112 from acw1251/pyosys_sigsig_issue
2019-08-24 Clifford WolfMerge pull request #1327 from YosysHQ/clifford/pmgen
2019-08-24 Eddie HungCreate new $__XILINX_SHREG_ cell for variable length too
2019-08-24 Eddie HungDo not allow Q of last cell of variable length SRL...
2019-08-24 Eddie HungAlso add first.Q to chain_bits since variable length
2019-08-24 Eddie HungDo not enforce !EN_POLARITY on $dffe
2019-08-24 Eddie HungCreate new cell for fixed length SRL
2019-08-24 Eddie HungCleanup FDRE matching
2019-08-23 Eddie HungOops don't need a finally block
2019-08-23 Eddie HungKeep track of bits in variable length chain, to check...
2019-08-23 Eddie HungDon't forget $dff has no EN
2019-08-23 Eddie HungSame for variable length
2019-08-23 Eddie HungFilter on en_port for fixed length
2019-08-23 Eddie HungCheck clock is consistent
2019-08-23 Eddie HungFix last_cell.D
2019-08-23 Eddie HungRevert "Add a unique argument to pmgen's nusers()"
2019-08-23 Eddie HungRevert "Fix polarity"
2019-08-23 Eddie HungFix polarity
2019-08-23 Eddie HungCheck for non unique nusers/fanouts
2019-08-23 Eddie HungAdd a unique argument to pmgen's nusers()
2019-08-23 Eddie HungUpdate doc
2019-08-23 Eddie HungRemove (* init *) entry when consumed into SRL
2019-08-23 Eddie Hungindo -> into
2019-08-23 Eddie Hungindo -> into
2019-08-23 Eddie HungForgot to slice
2019-08-23 Eddie HungCope with possibility that D could connect to Q on...
2019-08-23 Eddie Hungxilinx_srl to use 'slice' features of pmgen for word...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgen...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-23 Eddie HungMerge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 Eddie HungMerge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 Eddie Hungclkbufmap to only check clkbuf_inhibit if no selection...
2019-08-23 Eddie HungReview comment from @cliffordwolf
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into mwk...
2019-08-23 Clifford WolfFix port hanlding in pmgen
2019-08-23 Clifford WolfAdd pmgen slices and choices
2019-08-23 SergeyMerge pull request #1 from YosysHQ/Sergey/tests_ice40
2019-08-22 Eddie HungIn sat: 'x' in init attr should not override constant
2019-08-22 Eddie HungIn sat: 'x' in init attr should not override constant
2019-08-22 Eddie HungActually, there might not be any harm in updating sigmap...
2019-08-22 Eddie HungAdd comment as per @cliffordwolf
2019-08-22 Eddie HungRevert "Try way that doesn't involve creating a new...
2019-08-22 Eddie HungTry way that doesn't involve creating a new wire
2019-08-22 Eddie HungIf d_bit already in sigbit_chain_next, create extra...
2019-08-22 Eddie HungSpelling
2019-08-22 Eddie HungSpelling
2019-08-22 Eddie HungAdd doc
2019-08-22 Eddie HungMerge pull request #1319 from TeaEngineering/shuckc...
2019-08-22 Eddie HungAdd copyright
2019-08-22 Eddie HungRemove `shregmap -tech xilinx` additions
2019-08-22 Eddie Hungpmgen to also iterate over all module ports
2019-08-22 Eddie HungRemove output_bits
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