Fix write_aiger bug added in 524af21
[yosys.git] / passes /
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-19 Miodrag MilanovićMerge pull request #1457 from xobs/python-binary-name
2019-10-19 Sean CrossMakefile: don't assume python is called `python3`
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-16 Clifford WolfMerge pull request #1450 from YosysHQ/clifford/fixdffmux
2019-10-16 Clifford WolfFix dffmux peepopt init handling
2019-10-16 Clifford WolfMove GENERATE_PATTERN macro to separate utility header
2019-10-16 Clifford WolfDisable left-over log_debug in peepopt_dffmux.pmg
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-08 Eddie HungRevert "Be mindful that sigmap(wire) could have dupes...
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-06 Clifford WolfMerge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
2019-10-05 Eddie HungMissing 'accept' at end of ice40_wrapcarry, spotted...
2019-10-05 Clifford WolfUpdate README.md
2019-10-05 Eddie HungMissed this
2019-10-05 Eddie HungAdd comment on why we have to match for clock-enable...
2019-10-05 Eddie HungAdd note on pattern detector
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comments for xilinx_dsp_cascade
2019-10-05 Eddie HungImprove comments for xilinx_dsp_CREG
2019-10-05 Eddie HungFix comment
2019-10-05 Eddie HungRestore optimisation for sigM.empty()
2019-10-05 Eddie HungRetry on fixing TODOs
2019-10-05 Eddie HungRevert "Fix TODOs"
2019-10-05 Eddie HungMore comments, cleanup
2019-10-05 Eddie HungFix TODOs
2019-10-05 Eddie HungConsistency
2019-10-05 Eddie HungAdd comments for xilinx_dsp
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-04 Eddie HungFix xilinx_dsp for unsigned extensions
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungAdd -async2sync to help text as per @daveshah1
2019-10-04 Miodrag MilanovicFixes for MSVC build
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/efinix' of https://github...
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/anlogic' of https://github...
2019-10-03 Eddie HungRestore part of doc
2019-10-03 Eddie HungAdd new -async2sync option
2019-10-03 Eddie HungRevert "equiv_opt to call async2sync when not -multiclo...
2019-10-03 Eddie HungRevert "Update doc for equiv_opt"
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 Clifford WolfAdd "check -allow-tbuf"
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-03 Eddie HungFix broken CI, check reset even for constants, trim...
2019-10-03 Eddie HungMerge pull request #1423 from YosysHQ/eddie/techmap_rep...
2019-10-03 Eddie HungMerge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-03 Eddie HungRefactor peepopt_dffmux and be sensitive to \init when...
2019-10-02 Eddie HungBe mindful that sigmap(wire) could have dupes when...
2019-10-02 Eddie HungAlso rename cells with _TECHMAP_REPLACE_. prefix, as...
2019-10-02 Clifford WolfAdd "check -mapped"
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 Eddie Hungtechmap wires named _TECHMAP_REPLACE_.<identifier>...
2019-09-30 Eddie HungAdd -select option to aigmap
2019-09-30 Eddie HungMerge branch 'SergeyDegtyar/ecp5' of https://github...
2019-09-30 Eddie HungUpdate doc for equiv_opt
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Clifford WolfMerge pull request #1417 from YosysHQ/clifford/fixasync...
2019-09-30 Clifford WolfFix $dlatch handling in async2sync
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Miodrag MilanovicOpen aig frontend as binary file
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-27 Eddie Hungequiv_opt to call async2sync when not -multiclock like...
2019-09-27 Eddie HungOoops AREG and BREG to default to -1
2019-09-27 Marcin KościelnickiFix _TECHMAP_REMOVEINIT_ handling.
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-26 Eddie HungUpdate doc with max cascade chain of 20
2019-09-26 Eddie HungDo not always zero out C (e.g. during cascade breaks)
2019-09-26 Eddie HungUpdate doc
2019-09-26 Eddie HungZero out ports
2019-09-26 Eddie Hungxilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 Eddie HungTry recursive pmgen for P cascade
2019-09-26 Eddie HungCREG to check for \keep
2019-09-26 Eddie HungRemove newline
2019-09-26 Eddie HungDo not die if DSP48E1.P has no users (would otherwise...
2019-09-26 Eddie HungReject if (* init *) present
2019-09-26 Eddie HungRework xilinx_dsp postAdd for new wreduce call
2019-09-25 Eddie HungFix memory issue since SigSpec& could be invalidated
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
2019-09-25 Eddie Hungunextend only used in init
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Clifford WolfMerge pull request #1402 from YosysHQ/clifford/portlist
2019-09-25 Clifford WolfImprove "portlist" command
2019-09-24 Clifford WolfAdd "portlist" command
2019-09-24 Eddie Hung"abc_padding" attr for blackbox outputs that were padde...
2019-09-23 Eddie HungSet [AB]CASCREG to legal values
2019-09-23 Eddie HungComment to explain separating CREG packing
2019-09-23 Eddie HungSeparate out CREG packing into new pattern, to avoid...
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