write_xaiger to support part-selected modules again
[yosys.git] / passes /
2019-12-06 Eddie Hungabc9 to do clock partitioning again
2019-12-06 Eddie HungRemove clkpart
2019-12-04 Eddie HungAdd assertion
2019-12-04 Eddie HungAdd abc9_init wire, attach to abc9_flop cell
2019-12-02 Eddie HungCleanup
2019-12-02 Eddie HungUse pool instead of std::set for determinism
2019-12-02 Eddie HungUse pool<> not std::set<> for determinism
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-28 Eddie HungMove \init signal for non-port signals as long as inter...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungDo not replace constants with same wire
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungCleanup
2019-11-27 Eddie HungCheck for nullptr
2019-11-27 Eddie HungStray log_dump
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungPromote output wires in sigmap so that can be detected
2019-11-27 Eddie HungFix submod -hidden
2019-11-27 Eddie HungAdd -hidden option to submod
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-27 Eddie HungCheck for either sign or zero extension for postAdd...
2019-11-26 Eddie HungFix submod -hidden
2019-11-26 Eddie Hungclkpart to use 'submod -hidden'
2019-11-26 Eddie HungAdd -hidden option to submod
2019-11-26 Eddie HungUpdate docs with bullet points
2019-11-26 Eddie HungMove \init from source wire to submod if output port
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Eddie HungFix debug
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Eddie Hungabc9 to contain time call
2019-11-25 Eddie Hungabc9 to no longer to clock partitioning, operate on...
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMore oopsies
2019-11-23 Eddie HungConditioning abc9 on POs not accurate due to cells
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungPrint ".en=" only if there is an enable signal
2019-11-23 Eddie HungEscape IdStrings
2019-11-23 Eddie HungMore sane naming of submod
2019-11-23 Eddie HungAdd -set_attr option, -unpart to take attr name
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungDo not use log_signal() for empty SigSpec to prevent...
2019-11-23 Eddie HungCall submod once, more meaningful submod names, ignore...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie Hungsubmod to bitty rather bussy, for bussy wires used...
2019-11-23 Eddie HungMove clkpart into passes/hierarchy
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungConstant driven signals are also an input to submodules
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungOops
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungOnly action if there is more than one clock domain
2019-11-23 Eddie HungReplace TODO
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie Hungsigmap(wire) should inherit port_output status of POs
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungBrackets
2019-11-22 Eddie HungEntry in Makefile.inc
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungNew 'clkpart' to {,un}partition design according to...
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-22 Clifford WolfMerge pull request #1517 from YosysHQ/clifford/optmem
2019-11-22 Clifford WolfAdd "opt_mem" pass
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-11-22 Eddie HungWhen expanding upwards, do not capture $__ABC9_{FF...
2019-11-22 Eddie HungMerge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 David Shahproc_dlatch: Add error handling for incorrect always_...
2019-11-20 Eddie Hungendomain -> ctrldomain
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-18 David Shahmemory_collect: Copy attr from RTLIL::Memory to cell
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-14 David Shahwreduce: Don't trim zeros or sext when not matching...
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-13 Clifford WolfMerge pull request #1486 from YosysHQ/clifford/fsmdetectfix
2019-11-12 Clifford WolfUpdate fsm_detect bugfix
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