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Move much closer to new platform-M memory map
[riscv-isa-sim.git]
/
riscv
/
processor.cc
2016-04-29
Andrew Waterman
Move much closer to new platform-M memory map
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2016-04-28
Andrew Waterman
Remove MTIME[CMP]; add RTC device
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2016-04-06
Andrew Waterman
Remove non-standard uarch CSRs
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2016-03-17
Andrew Waterman
Update definition of base field in misa register
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2016-03-04
Andrew Waterman
Fix up interrupt delegation
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2016-03-02
Andrew Waterman
Add counter-enable registers
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2016-03-02
Andrew Waterman
New definitions of misa/marchid/mvendorid
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2016-03-02
Andrew Waterman
implement PUM functionality
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2016-03-02
Andrew Waterman
sptbr now a holds a PPN, not an address
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2016-03-02
Andrew Waterman
Use simpler MTVEC scheme
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2016-03-02
Andrew Waterman
Zero-extend all CSR writes
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2016-03-02
Andrew Waterman
Fix ERET serialization strategy
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2016-01-13
Andrew Waterman
don't ignore data value when writing MIPI
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2015-11-13
Andrew Waterman
Generate device tree for target machine
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2015-10-26
Andrew Waterman
Fix histogram for RVC
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2015-09-11
Andrew Waterman
Simplify register_base_instructions
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2015-09-11
Andrew Waterman
Initialize mstatus.prv1/prv2 to U, not S
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2015-09-11
Andrew Waterman
Support 'G' in ISA strings
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2015-09-09
Andrew Waterman
Improve instruction fetch
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2015-07-30
Christopher Celio
Added error message when trying to use histogram
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2015-07-05
Andrew Waterman
New machine-mode timer facility
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2015-06-01
Andrew Waterman
Use single, shared real-time counter
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2015-06-01
Andrew Waterman
Execute exactly the # of insns passed to step()
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2015-06-01
Andrew Waterman
Fix performance bug when CSR accesses are common
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2015-06-01
Andrew Waterman
Take interrupts as soon as interrupts are enabled
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2015-05-09
Andrew Waterman
Upgrade to privileged architecture 1.7
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2015-04-30
Andrew Waterman
Fix commit log for CSR instructions
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2015-04-04
Andrew Waterman
Check for F extension when accessing FCSR
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2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2015-03-31
Andrew Waterman
Allow writing mstatus.fs even if FPU isn't present
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2015-03-27
Andrew Waterman
Serialize counters without throwing C++ exceptions
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2015-03-26
Andrew Waterman
Update state.pc on every instruction
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2015-03-17
Yunsup Lee
bugfix, mbadaddr should be writable
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2015-01-27
Christopher Celio
Fixed masking/casting logic in commit log printf.
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2015-01-26
Andrew Waterman
Fix commit log
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2015-01-02
Andrew Waterman
Reduce dependences on auto-generated code
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2014-12-05
Andrew Waterman
Support 2/4/6/8-byte instructions
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2014-12-01
Andrew Waterman
Implement timer faithfully
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2014-08-15
Christopher Celio
Added PC histogram option.
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2014-08-08
Andrew Waterman
Support uarch counters (degenerately)
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2014-07-08
Andrew Waterman
Disallow access to FCSR when FP is disabled
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2014-07-07
Andrew Waterman
Minor refactoring
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2014-06-13
Christopher Celio
Commit log now prints while interrupts are enabled.
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2014-06-13
Andrew Waterman
Only print commit log if instruction commits
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2014-06-12
Andrew Waterman
Set status.u64 to true on boot
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2014-04-03
Stephen Twigg
Merge branch 'tm'
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2014-03-18
Andrew Waterman
Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
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2014-03-15
Andrew Waterman
speed up compilation a bit
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2014-02-14
Andrew Waterman
Fix I$ simulator not making forward progress
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2014-02-12
Andrew Waterman
Fix commit log when !debug
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2014-02-07
Andrew Waterman
Clear EVEC LSBs, which kindly prevents a segfault
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2014-01-24
Andrew Waterman
Handle CSR permissions correctly
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-16
Andrew Waterman
Initialize tohost and fromhost to zero
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-12-17
Andrew Waterman
Speed things up quite a bit
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-19
Yunsup Lee
clean up SR_EA, the enable accelerator bit in status reg
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-16
Yunsup Lee
fix missing null check when there's no extension
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2013-10-15
Stephen Twigg
Propogate the reset call to the extensions as well...
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2013-09-27
Christopher Celio
Added commit logging (--enable-commitlog). Also fixed...
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2013-09-23
Scott Beamer
fixes compile bug for not being able to find std::logic...
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2013-09-11
Andrew Waterman
Implement zany immediates
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2013-08-18
Andrew Waterman
Renumber PCRs
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2013-07-27
Andrew Waterman
New supervisor mode
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2013-07-27
Andrew Waterman
Remove more vector stuff
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2013-07-26
Andrew Waterman
Rip out Hwacha for now
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2013-07-26
Andrew Waterman
Rip out RVC for now
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2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-22
Andrew Waterman
Add xspike program
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2013-04-25
Andrew Waterman
use inttypes macros to print uint64_t
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2013-04-24
Yunsup Lee
fixes to correctly simulate the vector unit
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2013-03-30
Andrew Waterman
add load-reserved/store-conditional instructions
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2013-03-30
Andrew Waterman
ignore writes to SR IP field
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2013-03-26
Andrew Waterman
add BSD license
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2013-03-26
Andrew Waterman
truncate effective addresses in rv32
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2013-03-26
Andrew Waterman
expose pending interrupts in status register
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2013-02-13
Andrew Waterman
clean up fetch-execute loop a bit
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2012-11-13
Yunsup Lee
fix vector code simulation problem, turn on SR_U64
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2012-08-31
Andrew Waterman
new tohost/fromhost semantics
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2012-08-02
Andrew Waterman
new tohost/fromhost semantics
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2012-07-23
Andrew Waterman
correct HTIF reset behavior
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2012-05-09
Andrew Waterman
per-core tohost/fromhost registers
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2012-03-24
Andrew Waterman
new supervisor mode
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2012-03-20
Andrew Waterman
abstract regfile behind object
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2011-12-11
Yunsup Lee
fix utidx assign bug, make ut code execute faster
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2011-11-12
Your Name
Remove dependence on binutils
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2011-11-11
Andrew Waterman
Use new compiler toolchain's disassembler
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2011-11-11
Andrew Waterman
Changed supervisor mode
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-06-12
Andrew Waterman
[xcc] minor performance tweaks
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2011-06-12
Andrew Waterman
[xcc] fixed simulator build time
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