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Generate instruction decoder dynamically
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-22
Andrew Waterman
Add xspike program
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2013-06-03
Andrew Waterman
use coreutils `seq' instead of hacky `range'
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2013-05-15
Yunsup Lee
fix make issue
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2013-05-14
Yunsup Lee
change riscv-isa-run to spike
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2013-05-06
Andrew Waterman
make Makefile sh-friendly
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2013-04-25
Andrew Waterman
fix(?) circular dependence on generated headers
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2013-04-22
Andrew Waterman
correctly depend on dispatch.h
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2013-04-20
Andrew Waterman
remove circular dependence in Makefile
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2013-04-17
Andrew Waterman
add AUIPC insn; remove RDNPC insn
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2013-02-13
Andrew Waterman
add I$/D$/L2$ simulators
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2011-11-12
Your Name
Remove dependence on binutils
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-06-12
Andrew Waterman
[xcc] fixed simulator build time
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2011-06-11
Andrew Waterman
[sim, opcodes] made sim more decoupled from opcodes
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2011-05-29
Andrew Waterman
[sim,opcodes] improved sim build and run performance
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2011-05-16
Andrew Waterman
[sim,pk] cleanups & initial virtual memory support
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2011-04-15
Andrew Waterman
[sim] added icache simulator (disabled by default)
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2010-08-18
Andrew Waterman
[sim] integrated SoftFloat-3 with ISA sim; removed...
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2010-08-10
Andrew Waterman
[xcc,sim] implement FP using softfloat
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2010-08-10
Andrew Waterman
[sim] removed unused elf loader
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2010-07-22
Andrew Waterman
[pk,sim] first cut of appserver communication link
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2010-07-19
Andrew Waterman
Reorganized directory structure
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