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Refactor remote bitbang code.
[riscv-isa-sim.git]
/
riscv
/
sim.h
2017-02-03
Tim Newsome
OpenOCD connects, and sends some data that we receive.
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2016-06-23
Andrew Waterman
Remove legacy HTIF; implement HTIF directly
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2016-05-23
Tim Newsome
Have Debug memory kind of working again.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
Add -H to start halted.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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2016-05-02
Andrew Waterman
Remove tohost/fromhost registers
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2016-05-01
Andrew Waterman
Remove SCRs; add padding after config string
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2016-04-29
Andrew Waterman
Move much closer to new platform-M memory map
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2016-04-28
Andrew Waterman
Add --dump-config-string flag
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2016-04-28
Andrew Waterman
Remove MTIME[CMP]; add RTC device
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2016-03-02
Andrew Waterman
Use RV config string rather than FDT
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2015-11-13
Andrew Waterman
Generate device tree for target machine
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2015-09-25
Andrew Waterman
Refactor memory access code; add MMIO support
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2015-08-06
Andrew Waterman
Merge pull request #29 from pmundkur/devel
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2015-08-06
Prashanth Mundkur
Add an option (-l) to display a log of execution in...
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2015-06-06
Andrew Waterman
Merge pull request #25 from vapier/master
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2015-06-05
Mike Frysinger
add an interactive "pc" command
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2015-06-05
Mike Frysinger
unify interactive core processing
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2015-06-04
Andrew Waterman
Merge pull request #24 from vapier/master
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2015-06-04
Mike Frysinger
add a help screen to interactive mode
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2015-06-01
Andrew Waterman
Use single, shared real-time counter
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2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2014-08-15
Christopher Celio
Added PC histogram option.
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-29
Andrew Waterman
Pass target machine's return code back to OS
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-22
Andrew Waterman
Add xspike program
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2013-07-13
Andrew Waterman
Eliminate infinite loop in debug mode
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2013-07-13
Andrew Waterman
Exit cleanly from debug console
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2013-04-23
Andrew Waterman
destroy htif on simulator termination
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2013-03-30
Andrew Waterman
add load-reserved/store-conditional instructions
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2013-03-26
Andrew Waterman
add BSD license
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2013-02-13
Andrew Waterman
add I$/D$/L2$ simulators
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2013-01-26
Andrew Waterman
change htif to link against libfesvr
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2012-05-16
Andrew Waterman
fix htif interaction with interactive mode
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2012-05-09
Andrew Waterman
per-core tohost/fromhost registers
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2012-03-24
Andrew Waterman
new supervisor mode
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-06-12
Andrew Waterman
[xcc] minor performance tweaks
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2011-06-11
Andrew Waterman
[xcc] cleaned up mmu code
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2011-05-29
Andrew Waterman
[fesvr,xcc,sim] fixed multicore sim for akaros
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2011-05-01
Andrew Waterman
[sim] hacked in a dcache simulator
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2011-04-17
Andrew Waterman
[sim] added "str" debug command
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2011-04-15
Andrew Waterman
[sim] added icache simulator (disabled by default)
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2010-09-09
Andrew Waterman
Merge branch 'master' of /project/eecs/parlab/git/proje...
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2010-09-08
Yunsup Lee
[sim] add while to interactive_until
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2010-09-07
Andrew Waterman
[sim] fixed bug in msub.d; added ability to print FPRs...
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2010-08-10
Andrew Waterman
[sim] removed unused elf loader
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2010-07-22
Andrew Waterman
[pk,sim] first cut of appserver communication link
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2010-07-19
Andrew Waterman
Reorganized directory structure
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