git.libre-soc.org Git - binutils-gdb.git/history

2011-03-24	Mike Frysinger	sim: bfin: document SIC limitation	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: fix inverted W1C logic	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: define more UART LSR bits	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: fix typo in TWI stat reg	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: update VIT_MAX behavior to match hardware...	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: always do 16bit sign extension with the...	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: update AV and AC ASTAT bits with acc negation	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: fix thinko in SIC pin encoding	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: allow byteop[123]p src regs to be the same	tree \| commitdiff
2011-03-24	Mike Frysinger	sim: bfin: fix thinko in bfin_gpio bus addresses	tree \| commitdiff
2011-03-17	Mike Frysinger	sim: bfin: check for kill/pread	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: add GPIO device simulation	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: fix brace style	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: fix brace style	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: handle AZ updates with 16bit adds/subs	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: skip acc/ASTAT updates for moves	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: handle AN (negative overflows) in dsp mult...	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: handle V overflows in dsp mult insns	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: decode ASTAT on failure	tree \| commitdiff
2011-03-15	Mike Frysinger	sim: bfin: handle saturation with fract multiplications	tree \| commitdiff
2011-03-14	Mike Frysinger	sim: bfin: forgot to cvs add the changelog	tree \| commitdiff
2011-03-06	Mike Frysinger	sim: bfin: new port	tree \| commitdiff

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