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Merge pull request #178 from antonblanchard/intercon
[microwatt.git]
/
soc.vhdl
2020-06-02
Anton Blanchard
Merge pull request #178 from antonblanchard/intercon
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2020-05-25
Benjamin Herrenschmidt
irq: Simplify xics->core irq input
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2020-05-25
Benjamin Herrenschmidt
soc: Rework interconnect
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2020-05-25
Benjamin Herrenschmidt
sw: Add full memory map to .h and use it for litedram...
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2020-05-19
Anton Blanchard
Merge pull request #173 from Jbalkind/core-vcs-syntax
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2020-05-19
Anton Blanchard
Merge pull request #177 from antonblanchard/litedram
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2020-05-19
Anton Blanchard
Merge branch 'master' into litedram
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2020-05-19
Anton Blanchard
Merge pull request #176 from antonblanchard/console...
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2020-05-19
Anton Blanchard
Merge pull request #174 from antonblanchard/yosys-fixes
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2020-05-18
Anton Blanchard
Merge pull request #169 from paulusmack/mmu
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2020-05-16
Benjamin Herrenschmidt
soc/core: Add reset latches
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2020-05-16
Benjamin Herrenschmidt
litedram: Update to new LiteX/LiteDRAM version
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2020-05-14
Paul Mackerras
soc: Work around compile error with ghdl 0.37-dev
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2020-05-14
Paul Mackerras
Merge branch 'mmu'
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2020-05-14
Anton Blanchard
Merge pull request #170 from antonblanchard/litedram
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2020-05-09
Benjamin Herrenschmidt
litedram: Add support for Microwatt-initialized controller
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2020-05-08
Benjamin Herrenschmidt
syscon: Add syscon registers
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2020-05-08
Benjamin Herrenschmidt
soc: Add DRAM address decoding
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2020-05-08
Benjamin Herrenschmidt
core: Add alternate reset address
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2020-05-06
Paul Mackerras
Merge remote-tracking branch 'remotes/origin/master'
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2020-05-06
Anton Blanchard
Merge pull request #165 from mikey/xics
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2020-04-23
Michael Neuling
XICS interrupt controller
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2020-01-11
Anton Blanchard
Merge pull request #133 from antonblanchard/ghdl-synth
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2020-01-11
Anton Blanchard
Removed unused core_terminated signal
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2019-11-15
Anton Blanchard
Merge pull request #118 from antonblanchard/bus-pipeline
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2019-10-30
Benjamin Herrenschmidt
wb_arbiter: Make arbiter size parametric
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2019-10-30
Benjamin Herrenschmidt
ram: Rework main RAM interface
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2019-10-30
Benjamin Herrenschmidt
Add option to not flatten hierarchy
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2019-10-30
Benjamin Herrenschmidt
intercon: Generate stall signals for non-pipelined...
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2019-10-25
Anton Blanchard
Merge pull request #115 from antonblanchard/reduce...
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2019-10-23
Benjamin Herrenschmidt
Reduce wishbone address size to 32-bit
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2019-10-11
Anton Blanchard
Merge pull request #84 from classilla/master
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2019-10-11
Anton Blanchard
Merge pull request #89 from mikey/gitignore
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2019-10-10
Anton Blanchard
Merge pull request #86 from antonblanchard/outstanding...
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2019-10-10
Anton Blanchard
Merge pull request #85 from antonblanchard/leadingzeroe...
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2019-10-10
Anton Blanchard
Merge pull request #79 from deece/uart_address
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2019-10-08
Alastair D'Silva
Tighten UART address
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2019-09-24
Anton Blanchard
Merge branch 'divider' of https://github.com/paulusmack...
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2019-09-24
Anton Blanchard
Merge pull request #69 from antonblanchard/debug-module
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2019-09-20
Benjamin Herrenschmidt
Add core debug module
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2019-09-20
Benjamin Herrenschmidt
Add DMI address decoder
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2019-09-20
Benjamin Herrenschmidt
Wishbone debug module
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2019-09-20
Benjamin Herrenschmidt
Add a debug (DMI) bus and a JTAG interface to it on...
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2019-09-20
Benjamin Herrenschmidt
Use a 3 way WB arbiter and cleanup fpga toplevel
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2019-09-10
Benjamin Herrenschmidt
Switch soc to use std_ulogic
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2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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