mem-cache: Add multiple eviction stats
[gem5.git] / src / arch / arm / ArmISA.py
2019-11-25 Adrian Herreraarch-arm: default MIDR for Armv8 ISA processors
2019-08-05 Giacomo Travagliniarch-arm: Implement ARMv8.1-PAN, Privileged access...
2019-07-19 Giacomo Travagliniarch-arm: Implement ARMv8.1-HPD, Hierarchical permissio...
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global...
2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2016-12-19 Curtis Dunhamarm: compute ID_AA64PFR{0,1}_EL1 registers
2016-12-19 Curtis Dunhamarm: compute ID_PFR{0,1} registers
2016-08-02 Curtis Dunhamarm: enable EL2 support
2015-10-09 Rekai Gonzalez Alb... isa: Add parameter to pick different decoder inside ISA
2014-10-16 Andreas Sandbergarm: Add a model of an ARM PMUv3
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2013-01-07 Andreas Sandbergarm: Make ID registers ISA parameters
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject