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arm: Fixed undefined behaviours identified by gcc
[gem5.git]
/
src
/
arch
/
arm
/
intregs.hh
2014-04-29
Curtis Dunham
arm: use condition code registers for ARM ISA
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2014-09-03
Andrew Bardsley
arm: ISA X31 destination register fix
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2014-01-24
ARM gem5 Developers
arm: Add support for ARMv8 (AArch64 & AArch32)
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2012-03-19
Andreas Hansson
gcc: Clean-up of non-C++0x compliant code, first steps
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2011-05-13
Ali Saidi
ARM: Further break up condition code into NZ, C, V...
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2011-05-13
Ali Saidi
ARM: Remove the saturating (Q) condition code from...
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2011-05-13
Ali Saidi
ARM: Break up condition codes into normal flags, satura...
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2011-04-15
Nathan Binkert
includes: sort all includes
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2011-03-18
Ali Saidi
Automated merge with ssh://hg@repo.m5sim.org/m5
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2011-03-18
Matt Horsnell
ARM: Fix RFE macrop.
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2010-08-26
Gabe Black
ARM: Seperate out the renamable bits in the FPSCR.
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2010-06-02
Gabe Black
ARM: Allow flattening into any mode.
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2010-06-02
Gabe Black
ARM: Eliminate the unused rhi and rlo operands.
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2010-01-19
Derek Hower
merge
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2009-11-11
Gabe Black
Merge with the head.
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2009-11-11
Gabe Black
ARM: Fix the integer register indexes.
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2009-11-09
Nathan Binkert
automerge
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2009-11-08
Gabe Black
ARM: Support forcing load/store multiple to use user...
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2009-11-08
Gabe Black
ARM: Split the condition codes out of the CPSR.
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2009-11-08
Gabe Black
ARM: Add back in spots for Rhi and Rlo, and use a named...
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2009-11-08
Gabe Black
ARM: Set up an intregs.hh for ARM.
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