ARM: Break up condition codes into normal flags, saturation, and simd.
[gem5.git] / src / arch / arm / intregs.hh
2011-05-13 Ali SaidiARM: Break up condition codes into normal flags, satura...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Matt HorsnellARM: Fix RFE macrop.
2010-08-26 Gabe BlackARM: Seperate out the renamable bits in the FPSCR.
2010-06-02 Gabe BlackARM: Allow flattening into any mode.
2010-06-02 Gabe BlackARM: Eliminate the unused rhi and rlo operands.
2010-01-19 Derek Howermerge
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackARM: Fix the integer register indexes.
2009-11-09 Nathan Binkertautomerge
2009-11-08 Gabe BlackARM: Support forcing load/store multiple to use user...
2009-11-08 Gabe BlackARM: Split the condition codes out of the CPSR.
2009-11-08 Gabe BlackARM: Add back in spots for Rhi and Rlo, and use a named...
2009-11-08 Gabe BlackARM: Set up an intregs.hh for ARM.