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ARM: Further break up condition code into NZ, C, V bits.
[gem5.git]
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src
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arch
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arm
/
isa
/
insts
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str.isa
2011-05-13
Ali Saidi
ARM: Further break up condition code into NZ, C, V...
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2011-05-13
Ali Saidi
ARM: Break up condition codes into normal flags, satura...
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2011-03-18
Ali Saidi
Automated merge with ssh://hg@repo.m5sim.org/m5
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2011-03-18
Ali Saidi
ARM: Previous change didn't end up setting instFlags...
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2011-02-23
Matt Horsnell
ARM: Mark store conditionals as such.
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2010-11-15
Ali Saidi
ARM: Fix SRS instruction to micro-code memory operation...
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2010-08-26
Gene WU
ARM: Use fewer micro-ops for register update loads...
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2010-08-26
Ali Saidi
ARM: Fix VFP enabled checks for mem instructions
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2010-08-23
Ali Saidi
ARM: Exclusive accesses must be double word aligned
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2010-08-23
Gabe Black
ARM: Clean up the ISA desc portion of the ARM memory...
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2010-06-02
Ali Saidi
ARM: Implement the ARM TLB/Tablewalker. Needs performan...
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2010-06-02
Gabe Black
ARM: Implement the vstr instruction.
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2010-06-02
Gabe Black
ARM: Implement the SRS instruction.
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2010-06-02
Gabe Black
ARM: Implement the strex instructions.
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2010-06-02
Gabe Black
ARM: Respect the E bit of the CPSR when doing loads...
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2010-06-02
Gabe Black
ARM: Implement the V7 version of alignment checking.
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2010-06-02
Gabe Black
ARM: Explicitly keep track of the second destination...
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2010-06-02
Gabe Black
ARM: Remove the special naming for the new memory instr...
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2010-06-02
Gabe Black
ARM: Pull double memory instructions out of the decoder.
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2010-06-02
Gabe Black
ARM: Define the store instructions from outside the...
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