ARM: move kernel func event to correct location.
[gem5.git] / src / arch / arm / isa /
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Dam Sunwooutil: implements "writefile" gem5 op to export file...
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-10 Ali SaidiARM: Add support for initparam m5 op
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-12-01 Ali SaidiARM: Add IsSerializeAfter and IsNonSpeculative flag...
2011-11-02 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
2011-10-31 Gabe BlackGCC: Get everything working with gcc 4.6.1.
2011-09-27 Gabe BlackISA parser: Use '_' instead of '.' to delimit type...
2011-09-19 Gabe BlackPseudoInst: Remove the now unnecessary #if FULL_SYSTEMs...
2011-09-19 Gabe BlackPseudoinst: Add an initParam pseudo inst function.
2011-09-13 Chander SudanthiCP15 c15: enable execution with accesses to c15 registers
2011-08-19 Ali SaidiARM: Add support for DIV/SDIV instructions.
2011-08-19 Geoffrey BlakeFix bugs due to interaction between SEV instructions...
2011-07-15 Wade WalkerARM: Fix SWP/SWPB undefined instruction behavior
2011-07-05 Gabe BlackISA parser: Define operand types with a ctype directly.
2011-07-03 Nilay VaishMerged with Gabe's recent changes.
2011-07-03 Gabe BlackExecContext: Rename the readBytes/writeBytes functions...
2011-07-03 Gabe BlackISA: Use readBytes/writeBytes for all instruction level...
2011-06-17 Gedare BloomARM: Add m5ops and related support for workbegin()...
2011-05-18 Nathan Binkertgcc: fix an uninitialized variable warning from G+...
2011-05-13 Ali SaidiARM: Generate condition code setting code based on...
2011-05-13 Ali SaidiARM: Construct the predicate test register for more...
2011-05-13 Ali SaidiARM: Further break up condition code into NZ, C, V...
2011-05-13 Ali SaidiARM: Remove the saturating (Q) condition code from...
2011-05-13 Ali SaidiARM: Break up condition codes into normal flags, satura...
2011-05-05 Prakash RamrakhyaniARM: Implement WFE/WFI/SEV semantics.
2011-05-05 Ali SaidiARM: Fix small bug with vcvt instruction
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-04-04 Ali SaidiARM: Use CPU local lock before sending load to mem...
2011-04-04 Ali SaidiARM: Fix bug in MicroLdrNeon templates for initiateAcc().
2011-04-04 William WangARM: Cleanup and small fixes to some NEON ops to match...
2011-04-04 Ali SaidiARM: Cleanup implementation of ITSTATE and put importan...
2011-04-04 Ali SaidiARM: Fix m5op parameters bug.
2011-04-04 Ali SaidiARM: Tag appropriate instructions as IsReturn
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Fix subtle bug in LDM.
2011-03-18 Ali SaidiARM: Identify branches as conditional or unconditional...
2011-03-18 Ali SaidiARM: Fix small bug with VLDM/VSTM instructions.
2011-03-18 Ali SaidiARM: Allow conditional quiesce instructions.
2011-03-18 Matt HorsnellARM: Fix RFE macrop.
2011-03-18 Matt HorsnellARM: Rename registers used as temporary state by microops.
2011-03-18 Ali SaidiARM: Previous change didn't end up setting instFlags...
2011-02-23 Giacomo GabrielliARM: NEON instruction templates modified to set the...
2011-02-23 Ali SaidiARM: Squash state on FPSCR stride or len write.
2011-02-23 Matt HorsnellARM: Mark store conditionals as such.
2011-02-23 Ali SaidiARM: Do something for ISB, DSB, DMB
2011-02-23 Ali SaidiARM: Make Noop actually decode to a noop and set it...
2011-02-23 Ali SaidiARM: Adds dummy support for a L2 latency miscreg.
2011-01-18 Matt HorsnellO3: Fix itstate prediction and recovery.
2011-01-18 Matt HorsnellARM: The ARM decoder should not panic when decoding...
2011-01-18 Ali SaidiARM: Add support for moving predicated false dest opera...
2010-12-09 Gabe BlackARM: Take advantage of new PCState syntax.
2010-12-09 Gabe BlackARM: Get rid of some unused FP operands.
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
2010-12-08 Min Kyu JeongO3: Support SWAP and predicated loads/store in ARM.
2010-11-15 Giacomo GabrielliCPU/ARM: Add SIMD op classes to CPU models and ARM...
2010-11-15 Ali SaidiARM: Return an FailUnimp instruction when an unimplemen...
2010-11-15 Ali SaidiARM: Fix SRS instruction to micro-code memory operation...
2010-11-08 Ali SaidiARM: Add support for M5 ops in the ARM ISA
2010-11-08 Ali SaidiARM/Alpha/Cpu: Change prefetchs to be more like normal...
2010-11-08 Ali SaidiARM: Make all ARM uops delayed commit.
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-10-22 Gabe BlackISA: Simplify various implementations of completeAcc.
2010-10-22 Gabe BlackARM: Don't pretend to writeback registers in initiateAcc.
2010-10-13 Gabe BlackMem: Change the CLREX flag to CLEAR_LL.
2010-10-01 Ali SaidiARM: Clean up use of TBit and JBit.
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-26 Min Kyu JeongARM: Adding a bogus fault that does nothing.
2010-08-26 Ali SaidiARM: Make VMSR, RFE PC/LR etc non speculative, and...
2010-08-26 Gene WUARM: Use fewer micro-ops for register update loads...
2010-08-26 Ali SaidiARM: Fix VFP enabled checks for mem instructions
2010-08-26 Gabe BlackARM: Seperate out the renamable bits in the FPSCR.
2010-08-26 Gabe BlackARM: Fix type comparison warnings in Neon.
2010-08-26 Gabe BlackARM: Implement CPACR register and return Undefined...
2010-08-26 Gabe BlackARM: Implement all ARM SIMD instructions.
2010-08-23 Gene WuARM: Implement DBG instruction that doesn't do much...
2010-08-23 Gene WuMEM: Make CLREX a first class request operation and...
2010-08-23 Gene WuARM: Don't write tracedata on writes, it might have...
2010-08-23 Gene WuARM: Implement CLREX init/complete acc methods
2010-08-23 Gene WuARM: Implement DSB, DMB, ISB
2010-08-23 Gene WuARM: Implement CLREX
2010-08-23 Gene WuARM: BX instruction can be contitional if last instruct...
2010-08-23 Min Kyu JeongARM: mark msr/mrs instructions as SerializeBefore/After
2010-08-23 Min Kyu JeongARM/O3: store the result of the predicate evaluation...
2010-08-23 Gene WuARM: Temporary local variables can't conflict with...
2010-08-23 Ali SaidiARM: Exclusive accesses must be double word aligned
2010-08-23 Ali SaidiARM: Decode neon memory instructions.
2010-08-23 Gabe BlackARM: Clean up the ISA desc portion of the ARM memory...
2010-08-23 Ali SaidiARM: Implement some more misc registers
2010-07-15 Gabe BlackARM: Make an SRS instruction with a bad mode cause...
2010-06-02 Min Kyu JeongARM: Fix IT state not updating when an instruction...
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