ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
[gem5.git] / src / arch / arm / isa.cc
2010-11-15 Ali SaidiARM: Cache the misc regs at the TLB to limit readMiscRe...
2010-11-08 Ali SaidiARM: Keep the warnings to a minimum.
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-10-01 Ali SaidiARM: Clean up use of TBit and JBit.
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-26 Ali SaidiARM: Set the high bits in the part number so it's consi...
2010-08-26 Ali SaidiARM: Fix VFP enabled checks for mem instructions
2010-08-26 Gabe BlackARM: Implement CPACR register and return Undefined...
2010-08-23 Min Kyu JeongARM: Clean up flattening for SPSR adding
2010-08-23 Gene WuARM: Get SCTLR TE bit from reset SCTLR
2010-08-23 Ali SaidiARM: We don't currently support ThumbEE exceptions...
2010-08-23 Ali SaidiARM: Implement some more misc registers
2010-06-03 Ali SaidiARM: Fix issue with m5.fast and ARM
2010-06-02 Dam SunwooARM: Added support for Access Flag and some CP15 regs...
2010-06-02 Gabe BlackARM: Move the ISA "clear" function into isa.cc.
2010-06-02 Gabe BlackARM: Implement support for the IT instruction and the...
2010-06-02 Ali SaidiARM: Some TLB bug fixes.
2010-06-02 Ali SaidiARM: Move Miscreg functions out of isa.hh
2009-07-10 Gabe BlackARM: Fold the MiscRegFile all the way into the ISA...
2009-07-09 Gabe BlackRegisters: Add an ISA object which replaces the MiscReg...