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cpu, arch, arch-arm: Wire unused VecElem code in the O3 model
[gem5.git] / src / arch / arm / isa.hh
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the... blob | commitdiff | raw
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference. blob | commitdiff | raw | diff to current
2019-01-22 Gabe Blackarm: Get rid of some register type definitions. blob | commitdiff | raw | diff to current
2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem blob | commitdiff | raw | diff to current
2019-01-10 Jairo Balartdev-arm: Add a GICv3 model blob | commitdiff | raw | diff to current
2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR blob | commitdiff | raw | diff to current
2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32... blob | commitdiff | raw | diff to current
2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter blob | commitdiff | raw | diff to current
2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode blob | commitdiff | raw | diff to current
2018-09-13 Earl OuFix SConstruct for asan build blob | commitdiff | raw | diff to current
2018-09-10 Andreas Sandbergarm: Add support for tracking TCs in ISA devices blob | commitdiff | raw | diff to current
2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL... blob | commitdiff | raw | diff to current
2018-04-18 Giacomo Travagliniarch-arm: Adding MiscReg Priv (EL1) global flag blob | commitdiff | raw | diff to current
2018-03-23 Giacomo Travagliniarch-arm: Distinguish IS TLBI from non-IS blob | commitdiff | raw | diff to current
2018-03-23 Giacomo Travagliniarch-arm: Created function for TLB ASID Invalidation blob | commitdiff | raw | diff to current
2018-03-12 Giacomo Travagliniarch-arm: Adding IPA-Based Invalidating instructions blob | commitdiff | raw | diff to current
2018-02-16 Giacomo Travagliniarch-arm: Arch regs and pseudo regs distinction blob | commitdiff | raw | diff to current
2018-01-29 Curtis Dunhamarch-arm: understandably initialize register permissions blob | commitdiff | raw | diff to current
2018-01-29 Curtis Dunhamarm: extend MiscReg metadata structures blob | commitdiff | raw | diff to current
2018-01-29 Curtis Dunhamarch-arm: understandably initialize register mappings blob | commitdiff | raw | diff to current
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file blob | commitdiff | raw | diff to current
2017-07-05 Rekai Gonzalez-Alb... cpu: Simplify the rename interface and use RegId blob | commitdiff | raw | diff to current
2016-12-19 Curtis Dunhamarm: miscreg refactoring blob | commitdiff | raw | diff to current
2016-12-19 Curtis Dunhamarm: update AArch{64,32} register mappings blob | commitdiff | raw | diff to current
2016-08-02 Curtis Dunhamarm: enable EL2 support blob | commitdiff | raw | diff to current
2015-10-09 Rekai Gonzalez Alb... isa: Add parameter to pick different decoder inside ISA blob | commitdiff | raw | diff to current
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c blob | commitdiff | raw | diff to current
2015-07-26 Nilay Vaishcpu: implements vector registers blob | commitdiff | raw | diff to current
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class blob | commitdiff | raw | diff to current
2015-05-23 Andreas Sandbergdev, arm: Refactor and clean up the generic timer model blob | commitdiff | raw | diff to current
2015-05-05 Andreas Hanssonarm: Remove unnecessary boot uncachability blob | commitdiff | raw | diff to current
2015-03-02 Andreas Sandbergarm: Don't truncate 16-bit ASIDs to 8 bits blob | commitdiff | raw | diff to current
2014-10-30 Ali Saidiautomated merge blob | commitdiff | raw | diff to current
2014-10-30 Ali Saidiarm: Fix multi-system AArch64 boot w/caches. blob | commitdiff | raw | diff to current
2014-10-16 Andreas Sandbergarm: Add a model of an ARM PMUv3 blob | commitdiff | raw | diff to current
2014-04-29 Curtis Dunhamarm: use condition code registers for ARM ISA blob | commitdiff | raw | diff to current
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32) blob | commitdiff | raw | diff to current
2014-01-24 Andreas Hanssonarch: Make all register index flattening const blob | commitdiff | raw | diff to current
2013-10-15 Yasuko Eckertcpu: add a condition-code register class blob | commitdiff | raw | diff to current
2013-02-19 Andreas Hanssonscons: Add warning for overloaded virtual functions blob | commitdiff | raw | diff to current
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376 blob | commitdiff | raw | diff to current
2013-01-07 Andreas Sandbergarch: Move the ISA object to a separate section blob | commitdiff | raw | diff to current
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject blob | commitdiff | raw | diff to current
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn... blob | commitdiff | raw | diff to current
2010-11-08 Ali SaidiARM: Add checkpointing support blob | commitdiff | raw | diff to current
2010-08-23 Min Kyu JeongARM: Clean up flattening for SPSR adding blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Move the ISA "clear" function into isa.cc. blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Some TLB bug fixes. blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Move Miscreg functions out of isa.hh blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan... blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Implement ARM CPU interrupts blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Make various bits of the FP control registers... blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Make MPIDR return 0 and ignore writes. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Set the value of the MVFR0 and MVFR1 registers. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Handle accesses to TLBTR. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Convert the CP15 registers from MPU to MMU. blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Add some support for wfi/wfe/yield/etc blob | commitdiff | raw | diff to current
2010-06-02 Ali SaidiARM: Add a traceflag to print cpsr blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Ignore attempts to disable coprocessors that aren... blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Allow flattening into any mode. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Make the MPUIR register report that 1 unified... blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Ignore/warn when CSSELR or CCSIDR are accessed. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Add support for the clidr register. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Implement a stub of CPACR. blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Actually write the value of sctlr in ISA.clear(). blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Implement a function to decode CP15 registers... blob | commitdiff | raw | diff to current
2010-06-02 Gabe BlackARM: Track the current ISA mode using the PC. blob | commitdiff | raw | diff to current
2010-01-19 Derek Howermerge blob | commitdiff | raw | diff to current
2009-11-15 Gabe BlackARM: Hook up the moded versions of the SPSR. blob | commitdiff | raw | diff to current
2009-11-11 Gabe BlackMerge with the head. blob | commitdiff | raw | diff to current
2009-11-11 Gabe BlackARM: Implement fault classes. blob | commitdiff | raw | diff to current
2009-11-09 Nathan Binkertautomerge blob | commitdiff | raw | diff to current
2009-11-08 Gabe BlackARM: Support forcing load/store multiple to use user... blob | commitdiff | raw | diff to current
2009-11-08 Gabe BlackARM: Add in more bits for the mon mode. blob | commitdiff | raw | diff to current
2009-11-08 Gabe BlackARM: Initialize processes in user mode. blob | commitdiff | raw | diff to current
2009-11-08 Gabe BlackARM: Implement the shadow registers using register... blob | commitdiff | raw | diff to current
2009-10-18 Brad Beckmannmerged with ISA event manager fix blob | commitdiff | raw | diff to current
2009-10-17 Gabe BlackISA: Fix compilation. blob | commitdiff | raw | diff to current
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5 blob | commitdiff | raw | diff to current
2009-07-31 Korey Sewellmerge mips fix and statetrace changes blob | commitdiff | raw | diff to current
2009-07-27 Gabe BlackARM: Initialize the CPSR so that we're in user mode. blob | commitdiff | raw | diff to current
2009-07-13 Derek Howermerge blob | commitdiff | raw | diff to current
2009-07-10 Gabe BlackARM: Fold the MiscRegFile all the way into the ISA... blob | commitdiff | raw | diff to current
2009-07-09 Gabe BlackRegisters: Collapse ARM and MIPS regfile directories. blob | commitdiff | raw | diff to current
2009-07-09 Gabe BlackRegisters: Add an ISA object which replaces the MiscReg... blob | commitdiff | raw | diff to current