arm: Remove unnecessary boot uncachability
[gem5.git] / src / arch / arm / miscregs.cc
2014-12-08 Andreas Sandbergarm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0
2014-10-30 Ali Saidiautomated merge
2014-10-30 Ali Saidiarm: Mark some miscregs (timer counter) registers at...
2014-09-02 Akash Bagdiaarm: Don't speculatively access most miscregisters.
2014-10-01 Andreas Hanssonarm: Use MiscRegIndex rather than int when flattening
2014-08-13 Dam Sunwooarm: change MISCREG_L2ERRSR to warn not fail
2014-05-09 Geoffrey Blakearm: Panics in miscreg read functions can be tripped...
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2013-10-31 Chander SudanthiARM: add support for TEEHBR access
2012-05-10 Ali Saidigem5: Fix a number of incorrect case statements
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-01 Matt HorsnellARM: Add limited CP14 support.
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2011-09-13 Chander SudanthiCP15 c15: enable execution with accesses to c15 registers
2011-09-13 Daniel JohnsonARM: Implement numcpus bits in L2CTLR register.
2011-02-23 Ali SaidiARM: Adds dummy support for a L2 latency miscreg.
2011-01-18 Matt HorsnellARM: The ARM decoder should not panic when decoding...
2010-08-23 Ali SaidiARM: Implement some more misc registers
2010-06-02 Ali SaidiARM: Some TLB bug fixes.
2010-06-02 Ali SaidiARM: Move Miscreg functions out of isa.hh
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-06-02 Gabe BlackARM: Convert the CP15 registers from MPU to MMU.
2010-06-02 Gabe BlackARM: Implement a function to decode CP15 registers...