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arm: Fixed undefined behaviours identified by gcc
[gem5.git]
/
src
/
arch
/
arm
/
miscregs.cc
2014-08-13
Dam Sunwoo
arm: change MISCREG_L2ERRSR to warn not fail
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2014-05-09
Geoffrey Blake
arm: Panics in miscreg read functions can be tripped...
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2014-01-24
ARM gem5 Developers
arm: Add support for ARMv8 (AArch64 & AArch32)
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2013-10-31
Chander Sudanthi
ARM: add support for TEEHBR access
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2012-05-10
Ali Saidi
gem5: Fix a number of incorrect case statements
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2012-03-19
Andreas Hansson
gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-01
Matt Horsnell
ARM: Add limited CP14 support.
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Koan-Sin Tan
clang: Enable compiling gem5 using clang 2.9 and 3.0
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2011-09-13
Chander Sudanthi
CP15 c15: enable execution with accesses to c15 registers
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2011-09-13
Daniel Johnson
ARM: Implement numcpus bits in L2CTLR register.
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2011-02-23
Ali Saidi
ARM: Adds dummy support for a L2 latency miscreg.
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2011-01-18
Matt Horsnell
ARM: The ARM decoder should not panic when decoding...
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2010-08-23
Ali Saidi
ARM: Implement some more misc registers
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2010-06-02
Ali Saidi
ARM: Some TLB bug fixes.
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2010-06-02
Ali Saidi
ARM: Move Miscreg functions out of isa.hh
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2010-06-02
Ali Saidi
ARM: Implement the ARM TLB/Tablewalker. Needs performan...
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2010-06-02
Gabe Black
ARM: Convert the CP15 registers from MPU to MMU.
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2010-06-02
Gabe Black
ARM: Implement a function to decode CP15 registers...
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