projects
/
gem5.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
CP15 c15: enable execution with accesses to c15 registers
[gem5.git]
/
src
/
arch
/
arm
/
miscregs.cc
2011-09-13
Chander Sudanthi
CP15 c15: enable execution with accesses to c15 registers
blob
|
commitdiff
|
raw
2011-09-13
Daniel Johnson
ARM: Implement numcpus bits in L2CTLR register.
blob
|
commitdiff
|
raw
|
diff to current
2011-02-23
Ali Saidi
ARM: Adds dummy support for a L2 latency miscreg.
blob
|
commitdiff
|
raw
|
diff to current
2011-01-18
Matt Horsnell
ARM: The ARM decoder should not panic when decoding...
blob
|
commitdiff
|
raw
|
diff to current
2010-08-23
Ali Saidi
ARM: Implement some more misc registers
blob
|
commitdiff
|
raw
|
diff to current
2010-06-02
Ali Saidi
ARM: Some TLB bug fixes.
blob
|
commitdiff
|
raw
|
diff to current
2010-06-02
Ali Saidi
ARM: Move Miscreg functions out of isa.hh
blob
|
commitdiff
|
raw
|
diff to current
2010-06-02
Ali Saidi
ARM: Implement the ARM TLB/Tablewalker. Needs performan...
blob
|
commitdiff
|
raw
|
diff to current
2010-06-02
Gabe Black
ARM: Convert the CP15 registers from MPU to MMU.
blob
|
commitdiff
|
raw
|
diff to current
2010-06-02
Gabe Black
ARM: Implement a function to decode CP15 registers...
blob
|
commitdiff
|
raw
|
diff to current