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misc: Merged release-staging-v19.0.0.0 into develop
[gem5.git]
/
src
/
arch
/
arm
/
miscregs.cc
2020-02-24
Bobby R. Bruce
misc: Merged release-staging-v19.0.0.0 into develop
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2020-02-19
Adrian Herrera
arch-arm: Fix CNTFRQ_EL0 permission bits
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2020-02-18
Gabe Black
arm: Delete authors lists from the arm files.
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2020-02-06
Jordi Vaquero
arch-arm: This commit adds Pointer Authentication feature.
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2020-02-05
Gabe Black
arm: Use static_cast to get access the ARM specific...
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2020-02-04
Adrian Herrera
arch-arm: AArch64 reg access HCR_EL2.E2H filter
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2019-11-18
Adrian Herrera
arch-arm: R/W interface to AArch32 HCR2 misc reg
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64...
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64...
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64...
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2019-09-06
Giacomo Travaglini
arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
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2019-09-06
Giacomo Travaglini
arch-arm: Add explicit AArch64 MiscReg banking
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2019-09-06
Giacomo Travaglini
arch-arm: SGI registers undecoded in AArch32
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2019-08-20
Giacomo Travaglini
arch-arm: Replace occ of opModeToEL(currOpMode/cpsr...
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2019-08-05
Giacomo Travaglini
arch-arm: Implement ARMv8.1-PAN, Privileged access...
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2019-03-14
Giacomo Gabrielli
arch-arm,cpu: Add initial support for Arm SVE
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2019-01-10
Jairo Balart
dev-arm: Add a GICv3 model
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2019-01-03
Curtis Dunham
arm: properly handle RES0/1 for SCTLRs
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2018-11-07
Giacomo Travaglini
arch-arm: Implement AArch32 RVBAR
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2018-10-26
Giacomo Travaglini
arch-arm: IMPDEF for SYS instruction with CRn = {11...
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2018-10-01
Giacomo Travaglini
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
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2018-07-16
Giacomo Travaglini
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
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2018-07-16
Giacomo Travaglini
arch-arm: Introduce RAS System Registers
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2018-06-06
Andreas Sandberg
dev, arm: Add support for HYP & secure timers
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2018-05-29
Giacomo Travaglini
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
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2018-05-29
Giacomo Travaglini
arch-arm: Remove unusued MISCREG_A64_UNIMPL
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2018-05-29
Giacomo Travaglini
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
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2018-05-29
Giacomo Travaglini
arch-arm: Implement ARMv8.1 TTBR1_EL2 register
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2018-05-08
Giacomo Travaglini
arch-arm: Map ID_x_EL1 registers to AArch32 version
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2018-04-19
Giacomo Travaglini
arch-arm: Add ARMv8.1 TTBR1_EL2 register
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2018-04-18
Chuan Zhu
arch-arm: Fix FPEXC32_EL2 to FPEXC mapping
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2018-04-17
Giacomo Travaglini
arch-arm: Fix secure MiscReg access when EL3 is not...
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2018-03-12
Giacomo Travaglini
arch-arm: Adding IPA-Based Invalidating instructions
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2018-03-12
Giacomo Travaglini
arch-arm: Implement missing aarch32 TLBI registers
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2018-02-16
Giacomo Travaglini
arch-arm: IMPLEMENTATION DEFINED register
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2018-02-07
Nikos Nikoleris
arch-arm: Fault when dc ivac is executed from EL0
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2018-02-07
Giacomo Travaglini
arch-arm: Change function name for banked miscregs
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2018-01-29
Curtis Dunham
arch-arm: understandably initialize register permissions
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2017-12-08
Giacomo Travaglini
arm: Change access permission in TPIDRURO and TPIDRURW
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2017-12-04
Gabe Black
misc: Rename misc.(hh|cc) to logging.(hh|cc)
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2017-12-01
Giacomo Travaglini
arm: Enable ns registers access in secure mode
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2017-11-09
Nikos Nikoleris
arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1
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2017-04-03
Nikos Nikoleris
arm: Don't panic when checking coprocessor read/write...
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2016-11-09
Brandon Potter
style: [patch 1/22] use /r/3648/ to reorganize includes
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2016-12-19
Curtis Dunham
arm: miscreg refactoring
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2016-08-02
Dylan Johnson
arm: warn not fail on use of missing miscreg CNTHCTL_EL2
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2016-08-02
Curtis Dunham
arm: enable EL2 support
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2015-05-26
Curtis Dunham
arm: implement the CONTEXTIDR_EL2 system reg.
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2015-05-23
Andreas Sandberg
dev, arm: Add virtual timers to the generic timer model
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2015-05-05
Giacomo Gabrielli
arm: enable DCZVA by default in SE mode
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2014-12-08
Andreas Sandberg
arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0
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2014-10-30
Ali Saidi
automated merge
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2014-10-30
Ali Saidi
arm: Mark some miscregs (timer counter) registers at...
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2014-09-02
Akash Bagdia
arm: Don't speculatively access most miscregisters.
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2014-10-01
Andreas Hansson
arm: Use MiscRegIndex rather than int when flattening
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2014-08-13
Dam Sunwoo
arm: change MISCREG_L2ERRSR to warn not fail
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2014-05-09
Geoffrey Blake
arm: Panics in miscreg read functions can be tripped...
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2014-01-24
ARM gem5 Developers
arm: Add support for ARMv8 (AArch64 & AArch32)
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2013-10-31
Chander Sudanthi
ARM: add support for TEEHBR access
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2012-05-10
Ali Saidi
gem5: Fix a number of incorrect case statements
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2012-03-19
Andreas Hansson
gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-01
Matt Horsnell
ARM: Add limited CP14 support.
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Koan-Sin Tan
clang: Enable compiling gem5 using clang 2.9 and 3.0
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2011-09-13
Chander Sudanthi
CP15 c15: enable execution with accesses to c15 registers
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2011-09-13
Daniel Johnson
ARM: Implement numcpus bits in L2CTLR register.
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2011-02-23
Ali Saidi
ARM: Adds dummy support for a L2 latency miscreg.
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2011-01-18
Matt Horsnell
ARM: The ARM decoder should not panic when decoding...
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2010-08-23
Ali Saidi
ARM: Implement some more misc registers
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2010-06-02
Ali Saidi
ARM: Some TLB bug fixes.
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2010-06-02
Ali Saidi
ARM: Move Miscreg functions out of isa.hh
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2010-06-02
Ali Saidi
ARM: Implement the ARM TLB/Tablewalker. Needs performan...
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2010-06-02
Gabe Black
ARM: Convert the CP15 registers from MPU to MMU.
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2010-06-02
Gabe Black
ARM: Implement a function to decode CP15 registers...
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