scons: Add warning for missing field initializers
[gem5.git] / src / arch / arm / miscregs.hh
2013-01-07 Andreas Sandbergarm: Remove the register mapping hack used when copying TCs
2012-09-25 Andreas Sandbergarm: Use a static_assert to test that miscRegName[...
2012-07-27 Anthony GutierrezARM: fix value of MISCREG_CTR returned by readMiscReg()
2012-06-05 Chander SudanthiARM: removed extra white space
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-01 Matt HorsnellARM: Add limited CP14 support.
2011-09-13 Daniel JohnsonARM: update TLB to set request packet ASID field
2011-09-13 Chander SudanthiCP15 c15: enable execution with accesses to c15 registers
2011-09-13 Daniel JohnsonARM: Implement numcpus bits in L2CTLR register.
2011-07-15 Wade WalkerARM: Add two unimplemented miscellaneous registers.
2011-05-13 Ali SaidiARM: Further break up condition code into NZ, C, V...
2011-05-13 Ali SaidiARM: Remove the saturating (Q) condition code from...
2011-05-13 Ali SaidiARM: Break up condition codes into normal flags, satura...
2011-05-13 Chander SudanthiARM: Better RealView/Versatile EB platform support.
2011-05-05 Ali SaidiARM: Add support for MP misc regs and broadcast flushes.
2011-04-04 Ali SaidiARM: Use CPU local lock before sending load to mem...
2011-04-04 Ali SaidiARM: Fix checkpoint restoration into O3 CPU and the...
2011-04-04 William WangARM: Cleanup and small fixes to some NEON ops to match...
2011-04-04 Ali SaidiARM: Cleanup implementation of ITSTATE and put importan...
2011-03-25 Gabe BlackArm: Add in a missing miscRegName.
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Implement the Instruction Set Attribute Registers...
2011-02-23 Ali SaidiARM: Adds dummy support for a L2 latency miscreg.
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
2010-11-15 Ali SaidiARM: Add comment about the organization of the IT state...
2010-08-26 Gabe BlackARM: Seperate out the renamable bits in the FPSCR.
2010-08-26 Gabe BlackARM: Implement CPACR register and return Undefined...
2010-08-23 Ali SaidiARM: Implement some more misc registers
2010-06-02 Dam SunwooARM: Added support for Access Flag and some CP15 regs...
2010-06-02 Gabe BlackARM: Implement support for the IT instruction and the...
2010-06-02 Ali SaidiARM: Some TLB bug fixes.
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-06-02 Ali SaidiARM: Implement ARM CPU interrupts
2010-06-02 Gabe BlackARM: Make MPIDR return 0 and ignore writes.
2010-06-02 Gabe BlackARM: Set the value of the MVFR0 and MVFR1 registers.
2010-06-02 Gabe BlackARM: Add support for VFP vector mode.
2010-06-02 Gabe BlackARM: Implement and update the DFSR and IFSR registers...
2010-06-02 Gabe BlackARM: Add in some missing SCTLR fields.
2010-06-02 Gabe BlackARM: Warn/ignore when TLB maintenance operations are...
2010-06-02 Gabe BlackARM: Handle accesses to TLBTR.
2010-06-02 Gabe BlackARM: Handle accesses to the DACR.
2010-06-02 Gabe BlackARM: Handle accesses to TTBR0 and TTBR1.
2010-06-02 Gabe BlackARM: Convert the CP15 registers from MPU to MMU.
2010-06-02 Ali SaidiARM: Add some support for wfi/wfe/yield/etc
2010-06-02 Ali SaidiARM: Move PC mode bits around so they can be used for...
2010-06-02 Gabe BlackARM: Update the set of FP related miscregs.
2010-06-02 Gabe BlackARM: Ignore attempts to disable coprocessors that aren...
2010-06-02 Gabe BlackARM: Ignore/warn on accesses to the DRBAR, DRACR, and...
2010-06-02 Gabe BlackARM: Allow access to the RGNR register.
2010-06-02 Gabe BlackARM: Make the MPUIR register report that 1 unified...
2010-06-02 Gabe BlackARM: Ignore/warn on accesses to the BPIALLIS and BPIALL...
2010-06-02 Gabe BlackARM: Ignore/warn when CSSELR or CCSIDR are accessed.
2010-06-02 Gabe BlackARM: Ignore/warn access to the bpimva registers.
2010-06-02 Gabe BlackARM: Ignore/warn on accesses to the dccmvac register.
2010-06-02 Gabe BlackARM: Ignore/warn on accesses to icimvau.
2010-06-02 Gabe BlackARM: Ignore/warn on iciallu.
2010-06-02 Gabe BlackARM: Ignore/warn on ICIALLUIS.
2010-06-02 Gabe BlackARM: Add support for the clidr register.
2010-06-02 Gabe BlackARM: Decode the unimplemented data barrier CP15 accesses.
2010-06-02 Gabe BlackARM: Implement a stub of CPACR.
2010-06-02 Gabe BlackARM: Decode the unimplemented cp15 instruction barrier.
2010-06-02 Gabe BlackARM: Ignore accesses to DCCIMVAC.
2010-06-02 Gabe BlackARM: Allow accesses to the software thread id registers.
2010-06-02 Gabe BlackARM: Allow accesses to the contextidr register.
2010-06-02 Gabe BlackARM: Warn about and ignore accesses to DCCISW.
2010-06-02 Gabe BlackARM: Implement a function to decode CP15 registers...
2010-06-02 Gabe BlackARM: Replace the "never" condition with the "unconditio...
2010-06-02 Gabe BlackARM: Track the current ISA mode using the PC.
2010-01-19 Derek Howermerge
2009-11-15 Gabe BlackARM: Define a mask to differentiate purely CPSR bits...
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackARM: Implement fault classes.
2009-11-08 Gabe BlackARM: Add in more bits for the mon mode.
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-07-31 Korey Sewellmerge mips fix and statetrace changes
2009-07-27 Gabe BlackARM: Add in spots for the VFP control registers.
2009-06-27 Gabe BlackARM: Fill out the printReg function.
2009-06-21 Gabe BlackARM: Pull some static code out of the isa desc and...