2019-11-18 |
Adrian Herrera | arch-arm: R/W interface to AArch32 HCR2 misc reg |
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2019-09-06 |
Giacomo Travaglini | arch-arm: Add explicit AArch64 MiscReg banking |
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2019-08-05 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1-PAN, Privileged access... |
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2019-03-14 |
Giacomo Gabrielli | arch-arm,cpu: Add initial support for Arm SVE |
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2019-01-10 |
Jairo Balart | dev-arm: Add a GICv3 model |
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2018-11-07 |
Giacomo Travaglini | arch-arm: Remove MISCREG commented numbers |
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2018-10-01 |
Giacomo Travaglini | arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register |
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2018-10-01 |
Giacomo Travaglini | arch-arm: Move MiscReg BitUnions into a separate header... |
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2018-09-13 |
Anouk Van Laer | arch-arm: Correction for address size in EL1&0 translation |
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2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce ARMv8.1 Virtual Timer System Registers |
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2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce RAS System Registers |
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2018-06-28 |
Andreas Sandberg | arch-arm: Fix incorrect t{0,1}sz field in TTBCR |
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2018-06-14 |
Giacomo Travaglini | arch-arm: Read APSR in User Mode |
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2018-05-29 |
Giacomo Travaglini | arch-arm: Remove unusued MISCREG_A64_UNIMPL |
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2018-05-29 |
Giacomo Travaglini | arch-arm: Add E2H bit to HCR_EL2 System register |
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2018-04-19 |
Giacomo Travaglini | arch-arm: Add ARMv8.1 TTBR1_EL2 register |
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2018-02-16 |
Giacomo Travaglini | arch-arm: IMPLEMENTATION DEFINED register |
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2018-02-16 |
Giacomo Travaglini | arch-arm: Arch regs and pseudo regs distinction |
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2018-02-07 |
Giacomo Travaglini | arch-arm: Change function name for banked miscregs |
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2017-04-03 |
Nikos Nikoleris | arm: Don't panic when checking coprocessor read/write... |
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2016-12-19 |
Curtis Dunham | arm: update AArch{64,32} register mappings |
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2016-08-02 |
Dylan Johnson | arm: add stage2 translation support |
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2016-06-02 |
Andreas Sandberg | arm: Rewrite ERET to behave according to the ARMv8 ARM |
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2015-05-26 |
Curtis Dunham | arm: implement the CONTEXTIDR_EL2 system reg. |
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2014-10-30 |
Ali Saidi | automated merge |
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2014-10-30 |
Ali Saidi | arm: Mark some miscregs (timer counter) registers at... |
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2014-10-01 |
Andreas Hansson | arm: Use MiscRegIndex rather than int when flattening |
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2014-04-29 |
Curtis Dunham | arm: use condition code registers for ARM ISA |
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2014-05-27 |
Curtis Dunham | arm: support 16kb vm granules |
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2014-01-24 |
ARM gem5 Developers | arm: Add support for ARMv8 (AArch64 & AArch32) |
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2013-10-31 |
Chander Sudanthi | ARM: add support for TEEHBR access |
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2013-01-07 |
Andreas Sandberg | arm: Remove the register mapping hack used when copying TCs |
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2012-09-25 |
Andreas Sandberg | arm: Use a static_assert to test that miscRegName[... |
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2012-07-27 |
Anthony Gutierrez | ARM: fix value of MISCREG_CTR returned by readMiscReg() |
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2012-06-05 |
Chander Sudanthi | ARM: removed extra white space |
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2012-03-19 |
Andreas Hansson | gcc: Clean-up of non-C++0x compliant code, first steps |
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2012-03-01 |
Matt Horsnell | ARM: Add limited CP14 support. |
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2011-09-13 |
Daniel Johnson | ARM: update TLB to set request packet ASID field |
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2011-09-13 |
Chander Sudanthi | CP15 c15: enable execution with accesses to c15 registers |
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2011-09-13 |
Daniel Johnson | ARM: Implement numcpus bits in L2CTLR register. |
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2011-07-15 |
Wade Walker | ARM: Add two unimplemented miscellaneous registers. |
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2011-05-13 |
Ali Saidi | ARM: Further break up condition code into NZ, C, V... |
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2011-05-13 |
Ali Saidi | ARM: Remove the saturating (Q) condition code from... |
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2011-05-13 |
Ali Saidi | ARM: Break up condition codes into normal flags, satura... |
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2011-05-13 |
Chander Sudanthi | ARM: Better RealView/Versatile EB platform support. |
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2011-05-05 |
Ali Saidi | ARM: Add support for MP misc regs and broadcast flushes. |
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2011-04-04 |
Ali Saidi | ARM: Use CPU local lock before sending load to mem... |
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2011-04-04 |
Ali Saidi | ARM: Fix checkpoint restoration into O3 CPU and the... |
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2011-04-04 |
William Wang | ARM: Cleanup and small fixes to some NEON ops to match... |
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2011-04-04 |
Ali Saidi | ARM: Cleanup implementation of ITSTATE and put importan... |
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2011-03-25 |
Gabe Black | Arm: Add in a missing miscRegName. |
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2011-03-18 |
Ali Saidi | Automated merge with ssh://hg@repo.m5sim.org/m5 |
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2011-03-18 |
Ali Saidi | ARM: Implement the Instruction Set Attribute Registers... |
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2011-02-23 |
Ali Saidi | ARM: Adds dummy support for a L2 latency miscreg. |
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2010-12-08 |
Giacomo Gabrielli | O3: Make all instructions that write a misc. register... |
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2010-11-15 |
Ali Saidi | ARM: Add comment about the organization of the IT state... |
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2010-08-26 |
Gabe Black | ARM: Seperate out the renamable bits in the FPSCR. |
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2010-08-26 |
Gabe Black | ARM: Implement CPACR register and return Undefined... |
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2010-08-23 |
Ali Saidi | ARM: Implement some more misc registers |
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2010-06-02 |
Dam Sunwoo | ARM: Added support for Access Flag and some CP15 regs... |
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2010-06-02 |
Gabe Black | ARM: Implement support for the IT instruction and the... |
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2010-06-02 |
Ali Saidi | ARM: Some TLB bug fixes. |
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2010-06-02 |
Ali Saidi | ARM: Implement the ARM TLB/Tablewalker. Needs performan... |
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2010-06-02 |
Ali Saidi | ARM: Implement ARM CPU interrupts |
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2010-06-02 |
Gabe Black | ARM: Make MPIDR return 0 and ignore writes. |
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2010-06-02 |
Gabe Black | ARM: Set the value of the MVFR0 and MVFR1 registers. |
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2010-06-02 |
Gabe Black | ARM: Add support for VFP vector mode. |
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2010-06-02 |
Gabe Black | ARM: Implement and update the DFSR and IFSR registers... |
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2010-06-02 |
Gabe Black | ARM: Add in some missing SCTLR fields. |
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2010-06-02 |
Gabe Black | ARM: Warn/ignore when TLB maintenance operations are... |
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2010-06-02 |
Gabe Black | ARM: Handle accesses to TLBTR. |
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2010-06-02 |
Gabe Black | ARM: Handle accesses to the DACR. |
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2010-06-02 |
Gabe Black | ARM: Handle accesses to TTBR0 and TTBR1. |
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2010-06-02 |
Gabe Black | ARM: Convert the CP15 registers from MPU to MMU. |
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2010-06-02 |
Ali Saidi | ARM: Add some support for wfi/wfe/yield/etc |
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2010-06-02 |
Ali Saidi | ARM: Move PC mode bits around so they can be used for... |
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2010-06-02 |
Gabe Black | ARM: Update the set of FP related miscregs. |
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2010-06-02 |
Gabe Black | ARM: Ignore attempts to disable coprocessors that aren... |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on accesses to the DRBAR, DRACR, and... |
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2010-06-02 |
Gabe Black | ARM: Allow access to the RGNR register. |
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2010-06-02 |
Gabe Black | ARM: Make the MPUIR register report that 1 unified... |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL... |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn when CSSELR or CCSIDR are accessed. |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn access to the bpimva registers. |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on accesses to the dccmvac register. |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on accesses to icimvau. |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on iciallu. |
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2010-06-02 |
Gabe Black | ARM: Ignore/warn on ICIALLUIS. |
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2010-06-02 |
Gabe Black | ARM: Add support for the clidr register. |
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2010-06-02 |
Gabe Black | ARM: Decode the unimplemented data barrier CP15 accesses. |
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2010-06-02 |
Gabe Black | ARM: Implement a stub of CPACR. |
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2010-06-02 |
Gabe Black | ARM: Decode the unimplemented cp15 instruction barrier. |
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2010-06-02 |
Gabe Black | ARM: Ignore accesses to DCCIMVAC. |
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2010-06-02 |
Gabe Black | ARM: Allow accesses to the software thread id registers. |
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2010-06-02 |
Gabe Black | ARM: Allow accesses to the contextidr register. |
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2010-06-02 |
Gabe Black | ARM: Warn about and ignore accesses to DCCISW. |
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2010-06-02 |
Gabe Black | ARM: Implement a function to decode CP15 registers... |
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2010-06-02 |
Gabe Black | ARM: Replace the "never" condition with the "unconditio... |
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2010-06-02 |
Gabe Black | ARM: Track the current ISA mode using the PC. |
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2010-01-19 |
Derek Hower | merge |
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