stats: update stats for mmap() change.
[gem5.git] / src / arch / arm / tlb.cc
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements
2015-09-30 Mitch Hayengaarm: Change TLB Software Caching
2015-08-21 Andreas Hanssonarm, mem: Remove unused CLEAR_LL request flag
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-06-21 Andreas Sandbergarm: Cleanup arch headers to remove dma_device.hh depen...
2015-05-26 Nathanael Premillieuarm: Make address translation faster with better caching
2015-05-05 Andreas Sandbergarm: Relax ordering for some uncacheable accesses
2015-05-05 Andreas Sandbergmem, cpu: Add a separate flag for strictly ordered...
2015-05-05 Andreas Hanssonarm: Remove unnecessary boot uncachability
2015-03-02 Andreas Hanssonarm: Share a port for the two table walker objects
2014-12-23 Andreas Sandbergarm: Raise an alignment fault if a PC has illegal alignment
2014-11-14 Andreas Hanssonarm: Fixes based on UBSan and static analysis
2014-10-30 Ali Saidiautomated merge
2014-10-30 Ali Saidiarm: Fix multi-system AArch64 boot w/caches.
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
2014-10-16 Andreas Sandbergarm: Add TLB PMU probes
2014-09-27 Andreas Hanssonarm: Fixed undefined behaviours identified by gcc
2014-09-12 Andrew Bardsleystyle: Fix line continuation, especially in debug messages
2014-05-09 Geoffrey Blakearch, arm: Preserve TLB bootUncacheability when switchi...
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2013-10-31 Prakash Ramrakhyanimem: Add privilege info to request class
2013-06-03 Andreas Sandbergarch: Create a method to finalize physical addresses
2013-02-15 Mrinmoy Ghosharm: fix a page table walker issue where a page could...
2013-01-07 Andreas Sandbergarm: Invalidate cached TLB configuration in drainResume
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Gabe BlackImplement Ali's review feedback.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-02 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
2011-10-16 Gabe BlackARM: Turn on the page table walker on ARM in SE mode.
2011-09-13 Daniel JohnsonARM: update TLB to set request packet ASID field
2011-08-19 Ali SaidiARM: Mark some variables uncacheable until boot all...
2011-06-16 Ali SaidiARM: Handle case where new TLB size is different from...
2011-06-16 Chander SudanthiARM: Fix memset on TLB flush and initialization
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-04 Ali SaidiARM: Fix table walk going on while ASID changes error
2011-02-23 Ali SaidiARM: Fix bug that let two table walks occur in parallel.
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2011-01-18 Matt HorsnellO3: Fixes the way prefetches are handled inside the...
2010-12-08 Ali SaidiARM: Support switchover with hardware table walkers
2010-11-15 Ali SaidiARM: Cache the misc regs at the TLB to limit readMiscRe...
2010-11-08 Ali SaidiARM: Add some TLB statistics for ARM
2010-11-08 Ali SaidiARM: Add checkpointing support
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-10-13 Gabe BlackMem: Change the CLREX flag to CLEAR_LL.
2010-10-01 Ali SaidiARM: Make the TLB a little bit faster by moving most...
2010-10-01 Ali SaidiARM: Implement functional virtual to physical address...
2010-08-23 Gene WuMEM: Make CLREX a first class request operation and...
2010-08-23 Gene WuARM: Make sure that software prefetch instructions...
2010-08-23 Gene WuARM: Fix Uncachable TLB requests and decoding of xn bit
2010-08-23 Gene WuARM: For non-cachable accesses set the UNCACHABLE flag
2010-08-23 Gene WuARM: Implement CLREX
2010-06-15 Nathan Binkertstats: only consider a formula initialized if there...
2010-06-02 Dam SunwooARM: Allow multiple outstanding TLB walks to queue.
2010-06-02 Ali SaidiARM TLB: Fix bug in memAttrs getting a bogus thread...
2010-06-02 Dam SunwooARM: Support table walks in timing mode.
2010-06-02 Dam SunwooARM: Added support for Access Flag and some CP15 regs...
2010-06-02 Ali SaidiARM: Some TLB bug fixes.
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-06-02 Ali SaidiARM: Start over with translation from Alpha code as...
2010-06-02 Gabe BlackARM: Implement and update the DFSR and IFSR registers...
2010-06-02 Gabe BlackARM: Warn about not implementing MPU translation, not...
2010-06-02 Gabe BlackARM: Implement the V7 version of alignment checking.
2010-06-02 Gabe BlackARM: Track the current ISA mode using the PC.
2010-01-19 Derek Howermerge
2009-11-18 Ali SaidiARM: Boilerplate full-system code.
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtClean up some inconsistencies with Request flags.
2009-04-21 Nathan BinkertAutomated merge with ssh://m5sim.org//repo/m5
2009-04-21 Nathan Binkertarm: Unify the ARM tlb. We forgot about this when...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-04-06 Stephen Hinesarm: add ARM support to M5