projects / gem5.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
base: Rename Section to Segment, and some of its members.
[gem5.git] / src / arch / arm /
2019-10-09 Gabe Blackbase: Rename Section to Segment, and some of its members. tree | commitdiff
2019-10-07 Gabe Blackfastmodel: Make CortexA76x1's interrupts use gem5's... tree | commitdiff
2019-10-07 Ciro Santillikvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR tree | commitdiff
2019-10-03 Giacomo Travagliniarch-arm: Annotate CM flag in AA64 CM Instructions tree | commitdiff
2019-10-03 Giacomo Travagliniarch-arm: Set CM bit in DataAbort tree | commitdiff
2019-10-02 Giacomo Travagliniarch-arm: Create helper for sending events (SEV) tree | commitdiff
2019-10-02 Gabe Blackfastmodel: Get rid of the back channel mem port in... tree | commitdiff
2019-10-02 Gabe Blackfastmodel: Implement a custom sendFunctional for Cortex... tree | commitdiff
2019-10-02 Gabe Blackfastmodel: Let the EVS set an attribute for getSendFunc... tree | commitdiff
2019-10-01 Gabe Blackfastmodel: Add a gem5Cpu attribute to the CortexA76x1. tree | commitdiff
2019-10-01 Gabe Blackfastmodel: Add a utility class which makes it easier... tree | commitdiff
2019-10-01 Gabe Blackfastmodel: Pull out and simplify the interrupt mechanis... tree | commitdiff
2019-09-27 Gabe Blackfastmodel: Add glue code which adapts fastmodels to... tree | commitdiff
2019-09-19 Giacomo Travagliniarch-arm: PSTATE.PAN changes should inval cached regs... tree | commitdiff
2019-09-18 Giacomo Travagliniarch-arm: Fix Data Abort ISS when caused by Atomic... tree | commitdiff
2019-09-18 Giacomo Travagliniarch-arm: ISV bit in DataAbort should check for transla... tree | commitdiff
2019-09-18 Giacomo Travagliniarch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2... tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64... tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64... tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64... tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: Add explicit AArch64 MiscReg banking tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: Use same template across all MSR inst tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: SySDC64 Instructions (CMO) using MiscRegIndex tree | commitdiff
2019-09-06 Ciro Santilliarch-arm: fix GDB stub after SVE tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: SGI registers undecoded in AArch32 tree | commitdiff
2019-09-06 Giacomo Travagliniarch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC... tree | commitdiff
2019-08-30 Giacomo Travagliniarm,kvm: Fix python imports from global namespace tree | commitdiff
2019-08-21 Ciro Santilliarch-arm, cpu: fix ARM ubsan build on GCC 7.4.0 tree | commitdiff
2019-08-21 Chun-Chen TK Hsuarch-arm: Fix implicit fallthrough build errors tree | commitdiff
2019-08-20 Giacomo Travagliniarch-arm: Replace occ of opModeToEL(currOpMode/cpsr... tree | commitdiff
2019-08-20 Giacomo Travagliniarch-arm: Replace direct use cpsr.el with currEL helper tree | commitdiff
2019-08-20 Giacomo Travagliniarch-arm: Overload currEL helper with CPSR argument tree | commitdiff
2019-08-20 Giacomo Travagliniarch-arm: Rewrite the currEL helper method to use opMod... tree | commitdiff
2019-08-12 Jordi Vaqueroarch-arm: Added LD/ST<op> atomic instruction family... tree | commitdiff
2019-08-12 Jordi Vaqueroarch-arm: Adding CAS/CASP AMO instr including new Typed... tree | commitdiff
2019-08-07 Jordi Vaqueroarch-arm: Add TypeAtomicOp class to be used by new... tree | commitdiff
2019-08-07 Jordi Vaqueroarch-arm: adding register control flags enabling LSE... tree | commitdiff
2019-08-05 Giacomo Travagliniarch-arm: Implement ARMv8.1-PAN, Privileged access... tree | commitdiff
2019-08-05 Giacomo Travagliniarch-arm: Rewrite MSR immediate instruction class tree | commitdiff
2019-07-27 Gabor Dozsaarch-arm: Fix reg dependency for SVE gather microops tree | commitdiff
2019-07-27 Gabor Dozsaarch-arm: Fix tracing code for SVE gather tree | commitdiff
2019-07-27 Javier Setoainarch-arm: Add SVE LD1RQ[BHWD] tree | commitdiff
2019-07-27 Adrià Armejacharch-arm: Fix decoding for SVE memory instructions tree | commitdiff
2019-07-27 Javier Setoainarch-arm: Add support for SVE load/store structures tree | commitdiff
2019-07-19 Giacomo Travagliniarch-arm: Implement ARMv8.1-HPD, Hierarchical permissio... tree | commitdiff
2019-07-19 Giacomo Travagliniarch-arm: Add HPD bit for TCR_EL2/EL3 tree | commitdiff
2019-07-19 Giacomo Travagliniarch-arm: Clean Fault generation when processing Long... tree | commitdiff
2019-07-18 Gabor Dozsaarch-arm: Add first-/non-faulting load instructions tree | commitdiff
2019-07-17 Giacomo Travagliniarch-arm: Use ExceptionLevel type in TlbEntry tree | commitdiff
2019-06-26 Anouk Van Laerarch, arm: Update miscRegs in getTE tree | commitdiff
2019-06-17 Giacomo Travagliniarch-arm: Move the memacc_code before op_wb in fp loads tree | commitdiff
2019-06-10 Ciro Santilliarch-arm: implement VMINNM scalar thumb tree | commitdiff
2019-06-07 Giacomo Travagliniarch-arm: Fix WalkerState,Descriptors default constructor tree | commitdiff
2019-05-31 Chun-Chen TK Hsuarm: Fix decoding of CRC32 instructions in thumb32 tree | commitdiff
2019-05-31 Giacomo Gabrielliarch-arm: Treat SVE prefetch instructions as no-ops tree | commitdiff
2019-05-30 Giacomo Gabrielliarch-arm: Add initial support for SVE gather/scatter... tree | commitdiff
2019-05-30 Gabe Blackarch, base, cpu, gpu, sim: Merge getMemProxy and getVir... tree | commitdiff
2019-05-30 Gabe Blackarch, base, sim: Demote (SE|FS)TranslatingPortProxy... tree | commitdiff
2019-05-30 Gabe Blackarch, base, sim: Replace Copy(String)?(In|Out) with... tree | commitdiff
2019-05-29 Ciro Santillisim-se: add a release parameter to Process.py tree | commitdiff
2019-05-29 Gabe Blackarch, base, dev, sim: Remove now unnecessary casts... tree | commitdiff
2019-05-29 Gabe Blackarm, mem: Move the SecurePortProxy subclass into it... tree | commitdiff
2019-05-24 Giacomo Travagliniarch-arm: Fix fallthrough when trapping at EL2 tree | commitdiff
2019-05-23 Giacomo Travagliniarch-arm: Trap virtual accesses to GICv3 SGI registers tree | commitdiff
2019-05-23 Giacomo Travagliniarch-arm: Expose haveGicv3CPUInterface to the ISA interface tree | commitdiff
2019-05-23 Giacomo Travagliniarch-arm: Change mcrMrc15TrapToHyp signature tree | commitdiff
2019-05-21 Brandon Pottersim-se: change syscall function signature tree | commitdiff
2019-05-18 Gabe Blackarm: Add an object file loader for linux and freebsd. tree | commitdiff
2019-05-17 Ciro Santilliarch-arm: implement VMINNM and VMAXNM scalar version tree | commitdiff
2019-05-17 Ciro Santilliarch-arm: implement VMINNM and VMAXNM SIMD version tree | commitdiff
2019-05-17 Ciro Santilliarch-arm: rename operands to match spec in isa/formats... tree | commitdiff
2019-05-14 Javier Buenoarch-arm: Do not check MustBeOne flag for TLB requests... tree | commitdiff
2019-05-11 Giacomo Gabrielliarch-arm: Add initial support for SVE contiguous loads... tree | commitdiff
2019-04-30 Gabe Blackarch: Stop using TheISA within the ISAs. tree | commitdiff
2019-04-29 Giacomo Travagliniarch-arm: Faults DebugFlag now printing inst opcode... tree | commitdiff
2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined tree | commitdiff
2019-04-28 Gabe Blackarch, sim: Simplify the AuxVector type. tree | commitdiff
2019-04-28 Gabe Blackmem: Remove the ISA specialized versions of port proxy... tree | commitdiff
2019-04-28 Gabe Blackmem: Minimize the use of MemObject. tree | commitdiff
2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64 tree | commitdiff
2019-04-26 Gabe Blackarm: Factor some repetition out of the ProcessInfo... tree | commitdiff
2019-04-25 Gabe Blackarm: Fix some style issues in stacktrace.cc. tree | commitdiff
2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations tree | commitdiff
2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations tree | commitdiff
2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU tree | commitdiff
2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt tree | commitdiff
2019-04-01 Andrea Mondellidev-arm: Correct cast of template parameter tree | commitdiff
2019-03-28 Javier Setoainarch-arm: Fix use of bitwise operators on booleans tree | commitdiff
2019-03-28 Giacomo Travagliniarch-arm: Fix index generation for VecElem operands tree | commitdiff
2019-03-25 Javier Setoainarch-arm: Add missing fall-through defaults tree | commitdiff
2019-03-22 Tiago Mucksim-se: Fixed initialization array size tree | commitdiff
2019-03-21 Andrea Mondellidev-arm: ambiguous use of getPort() tree | commitdiff
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using... tree | commitdiff
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE tree | commitdiff
2019-03-11 Ryan Gambordarch-arm: Fixing implicit fallthrough build errors tree | commitdiff
2019-03-01 Andrea Mondellimem-cache: alias to mem::getMasterPort in TLB class tree | commitdiff
2019-03-01 Ciro Santilliarch-arm: implement floating point aarch32 VCVTA family tree | commitdiff
2019-02-18 Giacomo Travagliniarch-arm: Move GICv3 detection at startup time tree | commitdiff
2019-02-13 Ayaz Akramsim-se: update the arm kernel version tree | commitdiff
next