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base: Rename Section to Segment, and some of its members.
[gem5.git] / src / arch / arm /
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global... tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64 tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU tree | commitdiff
2019-02-08 Ruben Ayrapetyanarch-arm: Fix initialization of PMU counters tree | commitdiff
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal. tree | commitdiff
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*. tree | commitdiff
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers tree | commitdiff
2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autoge... tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instru... tree | commitdiff
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the... tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64 tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32 tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on... tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions tree | commitdiff
2019-01-23 Gabe Blackarm: Replace MiscReg with RegVal in utility.(hh|cc). tree | commitdiff
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference. tree | commitdiff
2019-01-22 Gabe Blackarm: Get rid of some register type definitions. tree | commitdiff
2019-01-22 Ciro Santilliarch-arm: implement the GDB XML target description... tree | commitdiff
2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers tree | commitdiff
2019-01-22 Brandon Pottersim-se: add syscalls related to polling tree | commitdiff
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa... tree | commitdiff
2019-01-16 Gabe Blackarm: Make the fp register types 64 bits. tree | commitdiff
2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is... tree | commitdiff
2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction tree | commitdiff
2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem tree | commitdiff
2019-01-14 Gabe Blackarm: Stop using the FloatReg and FloatRegBits types. tree | commitdiff
2019-01-10 Javier Setoainsim-se, arch-arm: Add support for getdents64 tree | commitdiff
2019-01-10 Andreas Sandbergarch-arm, sim-se: Add support for TLS in clone tree | commitdiff
2019-01-10 Andreas Sandbergarch-arm, sim-se: Fix incorrect SP handling in clone tree | commitdiff
2019-01-10 Andreas Sandbergsim-se: Refactor clone to avoid most ifdefs tree | commitdiff
2019-01-10 Javier Setoainarch-arm, sim-se: Wire up syscalls needed for pthreads tree | commitdiff
2019-01-10 Jairo Balartdev-arm: Add a GICv3 model tree | commitdiff
2019-01-09 Ivan Pizarroarch-arm: Additional bits in misc ARM registers to... tree | commitdiff
2019-01-03 Curtis Dunhamarm: properly handle RES0/1 for SCTLRs tree | commitdiff
2018-12-20 Gabe Blackarch, cpu: Remove float type accessors. tree | commitdiff
2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode tree | commitdiff
2018-12-03 Ciro Santilliarch-arm: correctly set floats from GDB on aarch64 tree | commitdiff
2018-12-03 Ciro Santilliarch-arm: only change the pc address when GDB registers... tree | commitdiff
2018-12-03 Ciro Santilliarch-arm: fix the aarch64 GDB stub tree | commitdiff
2018-11-28 Nikos Nikolerisarch-arm: Add missing template declaration tree | commitdiff
2018-11-28 Rekai Gonzalez-Alb... cpu,arch-arm: Initialise data members tree | commitdiff
2018-11-28 Matteo Andreozziarch-arm: clang compilation fixes tree | commitdiff
2018-11-27 Gabe Blackarch, base, cpu, gpu, mem: Replace assert(0 or false... tree | commitdiff
2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instru... tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used... tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32... tree | commitdiff
2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers tree | commitdiff
2018-11-05 Anouk Van Laerarch, arm: Return s1Req upon fault in s2Lookup tree | commitdiff
2018-11-05 Anouk Van Laerarch, arm: Effect of AT instructions on descriptor... tree | commitdiff
2018-10-29 Ciro Santillisyscall_emul: implement arm openat tree | commitdiff
2018-10-29 Yuetsu Kodamaarch-arm: FIXUP for the add PRFM PST instruction commit tree | commitdiff
2018-10-26 yuetsu.kodamaarch-arm: We add PRFM PST instruction for arm tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11... tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour tree | commitdiff
2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1 tree | commitdiff
2018-10-19 Ciro Santilliarm: treat aarch64 hints as NOPs instead of panic tree | commitdiff
2018-10-19 Ciro Santilliarm: update hint instruction decoding to match ARMv8.5 tree | commitdiff
2018-10-17 Gabe Blackarch: Get rid of the unused type AnyReg. tree | commitdiff
2018-10-12 Ciro Santillisyscall_emul: update arm uname release to 3.7.0+ tree | commitdiff
2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter tree | commitdiff
2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES tree | commitdiff
2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA tree | commitdiff
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto AES tree | commitdiff
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto SHA tree | commitdiff
2018-10-08 Ciro Santillidev, arm: remove the RealViewEB platform tree | commitdiff
2018-10-08 Matteo Andreozziarch-arm: Mark ArmProcess method as override tree | commitdiff
2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs tree | commitdiff
2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64 tree | commitdiff
2018-10-02 Edmund Grimley Evansarch-arm: Add FP16 support introduced by Armv8.2-A tree | commitdiff
2018-10-02 Edmund Grimley Evansarch-arm: Add FP16 support and other primitives to... tree | commitdiff
2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions tree | commitdiff
2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register tree | commitdiff
2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header... tree | commitdiff
2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode tree | commitdiff
2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET tree | commitdiff
2018-09-19 Brandon Pottersyscall_emul: expand AuxVector class tree | commitdiff
2018-09-13 Earl OuFix SConstruct for asan build tree | commitdiff
2018-09-13 Anouk Van Laerarch-arm: Correction for address size in EL1&0 translation tree | commitdiff
2018-09-13 Anouk Van Laerarch-arm: Correction to address size in EL2/EL3 tree | commitdiff
2018-09-12 Ciro Santillidev-arm: rename Pl390 to GicV2 tree | commitdiff
2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin tree | commitdiff
2018-09-10 Andreas Sandbergarm: Use the interrupt adaptor in the PMU tree | commitdiff
2018-09-10 Andreas Sandbergarm: Add support for tracking TCs in ISA devices tree | commitdiff
2018-08-10 Giacomo Gabrielliarm: Add support for RCpc load-acquire instructions... tree | commitdiff
2018-08-02 Andreas Sandbergarch-arm: Don't fail to initialise PMU if BP is missing tree | commitdiff
2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers tree | commitdiff
2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers tree | commitdiff
2018-06-28 Andreas Sandbergarch-arm: Fix incorrect t{0,1}sz field in TTBCR tree | commitdiff
2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break tree | commitdiff
2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is imple... tree | commitdiff
2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32 tree | commitdiff
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