projects / gem5.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
arch-arm, dev-arm: Consistently use ISO prefixes
[gem5.git] / src / arch / arm /
2021-01-24 Andreas Sandbergarch-arm, dev-arm: Consistently use ISO prefixes tree | commitdiff
2021-01-23 Gabe Blackarch-arm: Stop "using namespace std" tree | commitdiff
2021-01-23 Giacomo Travagliniarch-arm: Fix Compare and Swap Pair instructions tree | commitdiff
2021-01-22 Andreas Sandbergarch-arm, dev-arm: Remove Python 2 compatibility code tree | commitdiff
2021-01-20 Gabe Blackarm: Use the "reg" ABI for gem5 ops. tree | commitdiff
2021-01-19 Gabe Blackarm: Export the mostly generic syscall ABI. tree | commitdiff
2021-01-19 Gabe Blackarm: Use local src and dest reg index arrays. tree | commitdiff
2021-01-18 Giacomo Travagliniarch-arm: dtb_addr is already encoding the loadAddrOffset tree | commitdiff
2021-01-13 Ciro Santilliarch-arm: inform bootloader of kernel position with... tree | commitdiff
2020-12-21 Gabe Blackscons,fastmodel: Change how ARM license slots are throt... tree | commitdiff
2020-12-16 Gabe Blackarm: Fix style in the ISA templates. tree | commitdiff
2020-12-11 muptonarm,kvm: missed rename of MISCREG_HYP in kvm/armv8_cpu.cc tree | commitdiff
2020-11-26 Ciro Santilliarch-arm: add official names to all PMU events tree | commitdiff
2020-11-26 Curtis Dunhamarch-arm: Add ID_MMFR4{,EL1} system registers tree | commitdiff
2020-11-26 Bobby R. BruceMerge "misc: Merge branch hotfix v20.1.0.2 branch into... tree | commitdiff
2020-11-25 Giacomo Travagliniarch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure... tree | commitdiff
2020-11-25 Giacomo Travagliniarch-arm: Add SECURE_RD/WR flags to miscRegInfo tree | commitdiff
2020-11-25 Ciro Santilliarch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister tree | commitdiff
2020-11-24 Gabe Blackarm: Use the common pseudoInst dispatch function. tree | commitdiff
2020-11-23 Ciro Santilliarch-arm: serialize miscregs as a map tree | commitdiff
2020-11-19 Giacomo Travaglinifastmodel: Replace xrange with range to be python3... tree | commitdiff
2020-11-19 Giacomo Travaglinifastmodel: Use BaseMMU in the CortexR52 wrapper tree | commitdiff
2020-11-17 Jordi Vaqueroarch-arm: Implementation ARMv8.1 RDMA tree | commitdiff
2020-11-17 Gabe Blackfastmodel: Wrap the PL330 DMA controller fast model. tree | commitdiff
2020-11-16 Bobby R. Brucemisc: Merge branch hotfix v20.1.0.2 branch into develop tree | commitdiff
2020-11-16 Ciro Santilliarch-arm: move serialize and unserialize definition... tree | commitdiff
2020-11-06 Gabe Blackarch,cpu: Enforce using accessors to get at src/destRegIdx. tree | commitdiff
2020-11-04 Gabe Blackarm: Get rid of some unused instruction templates. tree | commitdiff
2020-11-03 Giacomo Travagliniarch-arm: Do not use _flushMva for TLBI IPA tree | commitdiff
2020-11-03 Giacomo Travagliniarch-arm: TlbEntry flush to be considered as functional... tree | commitdiff
2020-11-03 Giacomo Travagliniarch-arm: Fix implementation of TLBI_VMALL instructions tree | commitdiff
2020-11-03 Giacomo Travagliniarch-arm: Add el2Enabled cached variable tree | commitdiff
2020-11-03 Giacomo Travaglinicpu, fastmodel: Remove the old getDTBPtr/getITBPtr... tree | commitdiff
2020-11-03 Yu-hsin Wangdev-arm: Fix VExpressFastmodel timer configs tree | commitdiff
2020-11-02 Giacomo Travaglinikvm, arm: Add parameter to force simulation of Gicv2 tree | commitdiff
2020-10-30 Gabe Blackmisc: Delete the now unnecessary create methods. tree | commitdiff
2020-10-29 Gabe Blackarch,sim: Handle KVM SE page faults with workload events. tree | commitdiff
2020-10-28 Gabe Blackarm: Implement an SE workload for Linux and FreeBSD. tree | commitdiff
2020-10-24 Gabe Blackfastmodel: Fix up for the new standardized create(... tree | commitdiff
2020-10-23 Giacomo Travagliniarch-arm: Fix implementation of TLBI ALLEx instructions tree | commitdiff
2020-10-23 Giacomo Travagliniarch-arm: Rewrite the TLB flushing interface tree | commitdiff
2020-10-23 Giacomo Travagliniarch-arm: Reimplement TLB::flushAll tree | commitdiff
2020-10-23 Giacomo Travagliniarch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for... tree | commitdiff
2020-10-23 Gabe Blackmisc: Replace enable_if<>::type with enable_if_t<>. tree | commitdiff
2020-10-21 Giacomo Travagliniarch-arm: Replace any getDTBPtr/getITBPtr usage tree | commitdiff
2020-10-21 Giacomo Travaglinimisc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB tree | commitdiff
2020-10-19 Gabe Blackmisc: Wrap __attribute__((aligned())) in a macro in... tree | commitdiff
2020-10-19 Gabe Blackmisc: Use compiler.hh macros when available. tree | commitdiff
2020-10-17 Giacomo Travagliniarch-arm: Implement ArmPMU DTB generation tree | commitdiff
2020-10-17 Giacomo Travaglinidev-arm, fastmodel: Rewrite Gic.interruptCells tree | commitdiff
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects. tree | commitdiff
2020-10-14 Jordi Vaqueroarch-arm: Implement Armv8.2-LPA tree | commitdiff
2020-10-14 Jordi Vaqueroarch-arm: Implement Armv8.2-LVA tree | commitdiff
2020-10-14 Gabe Blackfastmodel: Update to c++14, and add some missing consts. tree | commitdiff
2020-10-13 Gabe Blackfastmodel: Add a wrapper for the CortexR52. tree | commitdiff
2020-10-08 Giacomo Travagliniarch-arm: Default ArmSystem to AArch64 tree | commitdiff
2020-10-07 Giacomo Travaglinifastmodel: Add IrisMMU model tree | commitdiff
2020-10-07 Giacomo Travagliniarch: Add generic BaseMMU tree | commitdiff
2020-10-06 Hoa Nguyenarch-arm: Replace call to `tmpnam()` by a deterministic one tree | commitdiff
2020-10-06 Pierre Ayoubarch-arm: Add recursion for DTB entry generation inside... tree | commitdiff
2020-10-01 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into... tree | commitdiff
2020-09-30 Giacomo Travagliniarch-arm: Using new "raw" memhelpers tree | commitdiff
2020-09-29 Timothy Hayesarch-arm: Instantiate a single HTM checkpoint at ISA... tree | commitdiff
2020-09-28 Gabe Blackmisc: Update attribute syntax, and reorganize compiler.hh. tree | commitdiff
2020-09-28 Gabe Blackarch,base,cpu,dev: Get rid of the M5_DUMMY_RETURN macro. tree | commitdiff
2020-09-28 Gabe Blackarm,base,gpu: Use std::make_unique instead of m5::make_... tree | commitdiff
2020-09-25 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into... tree | commitdiff
2020-09-24 Gabe Blackfastmodel: Update the IRIS ThreadContext base class. tree | commitdiff
2020-09-24 Gabe Blackfastmodel: Update for the isa_traits.hh changes. tree | commitdiff
2020-09-22 Giacomo Travagliniarch-arm: TLBI ALLE2IS should broadcast to the IS domain tree | commitdiff
2020-09-22 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into... tree | commitdiff
2020-09-20 Gabe Blackarch,cpu,sim: Route system calls through the workload. tree | commitdiff
2020-09-17 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into... tree | commitdiff
2020-09-16 Gabe Blackarch,cpu: Get rid of the IsMemRef StaticInst flag. tree | commitdiff
2020-09-16 Gabe Blackarch,cpu: Rearrange StaticInst flags for memory barriers. tree | commitdiff
2020-09-16 Gabe Blackarm: Use zero initialization for the BigRegVect types. tree | commitdiff
2020-09-15 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into... tree | commitdiff
2020-09-13 Giacomo Travagliniarch-arm: Fix ArmISA namespace requirement for Arm KVM tree | commitdiff
2020-09-11 Jason Lowe-Powerarch-arm: Initialize some cases of destReg tree | commitdiff
2020-09-10 Shivani Parekhmisc: Replaced master/slave terminology tree | commitdiff
2020-09-10 Iru Caiarch-arm: just return the fault in twoEqualRegInst... tree | commitdiff
2020-09-10 Iru Caiarch-arm: Fix build errors with gcc 10.2 tree | commitdiff
2020-09-10 Gabe Blackfastmodel: Add an ISA class which defers to IRIS. tree | commitdiff
2020-09-10 Gabe Blackfastmodel: Create a fake "Interrupts" object for fast... tree | commitdiff
2020-09-09 Giacomo Travagliniarch-arm: Fix ArmISA namespace requirement for TME... tree | commitdiff
2020-09-08 Gabe Blackarm: Remove "using namespace ArmISA" from arch/arm... tree | commitdiff
2020-09-08 Timothy Hayesarch-arm: Transactional Memory Extension (TME) tree | commitdiff
2020-09-08 Gabe Blackarm: Replicate the PageBytes constant in the ArmSystem... tree | commitdiff
2020-09-08 Andreas Sandbergbase, sim: Make ByteOrder into a ScopedEnum accessible... tree | commitdiff
2020-09-02 Gabe Blackmisc: Remove the "fault" parameter from syscall functions. tree | commitdiff
2020-09-01 Bobby R. Brucearch-arm,arch-x86: Added missing overrides tree | commitdiff
2020-08-28 Giacomo Travagliniarch-arm: Fix coding style in addressTranslation methods tree | commitdiff
2020-08-28 Giacomo Travagliniarch-arm: Check if PAC is implemented before executing... tree | commitdiff
2020-08-28 Giacomo Travagliniarch-arm: Introduce HavePACExt helper tree | commitdiff
2020-08-26 Emily Brickeyarch: update port terminology tree | commitdiff
2020-08-26 Giacomo Travagliniarch-arm: Rewrite addressTranslation to use BitUnions tree | commitdiff
2020-08-26 Giacomo Travagliniarch-arm: Remove deadcode from AArch64 address translation tree | commitdiff
2020-08-26 Giacomo Travagliniarch-arm: Refactor Address Translation (AT) code tree | commitdiff
2020-08-25 Gabe Blackarm: Clear out isa_traits.hh. tree | commitdiff
2020-08-25 Gabe Blackarch: Get rid of (some) unused VAddr types. tree | commitdiff
next